Today, design verification is the single largest activity in the majority of project schedules. Because of the interaction between the growing number of functional units within an IC design, functional-verification complexity grows faster than design-density growth. Verification complexity increases exponentially with design size. The Electronic Design community has concluded that the only way to master increasingly complex verification is to move beyond the register-transfer level (RTL) of design abstraction and adopt new system-level languages.
This solution is being touted despite the fact that engineering organizations worldwide have heavily invested in resources and have trained designers to use current RTL-based tools and methodologies. Why should electronics designers move beyond RTL? Are the perceived benefits real, and if so, what are they?
Industry observers claim it's necessary because RTL simulation performance is the cause of the dreaded design-verification bottleneck. They argue it takes too long to verify RTL code, because of long execution runs and large test suites, and it takes too long to write RTL code instead of designing with a higher-level language code. Meanwhile, EDA software companies view the move beyond RTL as an opportunity to sell new tools and design methodologies, as well as to develop new markets.
I believe not enough has been done to resolve the RTL design-verification problem. In fact, I think this is where the industry's focus and attention should remain. Current system-level design-language proposals are more like libraries and functions to make C/C++ work, or look suspiciously like Verilog HDL. Advances in synthesis or analysis algorithms aren't available to help new design languages, which was the case 13 years ago with Verilog HDL.
The industry doesn't have a well-understood design abstraction beyond RTL. Domain-specific abstractions exist for DSP and networking. Therefore, behavioral synthesis works for specific architectures only. Designers still have to write RTL code. We don't need to add more layers to the design process, but instead shrink the existing ones.
Accurate performance analysis requires cycle-accurate modeling that's not currently available in system-level design tools. Abstraction will let designers manage design complexity, but it won't allow them to escape it. A higher abstraction level won't reduce design time if designers spend time rewriting code and tweaking software to get an acceptable quality of results.
New test languages are tackling the test-specification problem, for example, and making it easier than ever to generate huge test suites. While more tests can be written faster in these languages, the simulation time to execute tests grows proportionally to the generated test-suite size. This means breakthroughs in simulation performance are required. Simulation accelerators with fast compile times and high performance are perhaps the best solution to this problem, and the design-verification problem in general.
Moving beyond RTL won't solve design complexity problems. The electronics industry would be far better served by improving RTL and existing verification-language efficiencies. What if there was a better solution for RTL verification that uses the best and most optimized approaches for hardware and software domains? This solution would create an efficient link between domains and concentrate on verification bottlenecks. It would be a more practical solution than discarding existing resources and reinvesting in training.