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Intel Agilex FPGA Brings CXL to Embedded, Data-Center Apps

Intel Agilex FPGA Brings CXL to Embedded, Data-Center Apps

The Compute Express Link (CXL) is a key feature found with the new Agilex line—the FPGAs will mate CXL to host processors.

The new line of Agilex FPGAs developed by Intel delivers an impressive array of features, including support for the new Compute Express Link (CXL) standard design that puts devices on an equal footing with host processors. The family takes advantage of the company’s die-to-die interconnect, Embedded Multi-die Interconnect Bridge (EMIB), which was originally developed by Altera and is now part of Intel. EMIB allows Intel to mix EMIB-linked chiplets or tiles with support for high-speed transceivers, PCI Express (PCIe), and a quad-core ARM Cortex-A53 complex for the SoC edition (Fig. 1).

Agilex FPGA

1. The Agilex FPGA uses EMIB connectivity to blend its FPGA fabric with other devices, including processors, high-speed interfaces, and memory.

The Agilex is based on Intel’s 10-nm technology. It provides a 40% performance boost compared to the Intel Stratix 10 while reducing power by up to 40%. The top-end systems can deliver up to 40 TFLOPS (FP16 performance) using the new DSP blocks, and are designed to handle DDR5 and provide on-chip high bandwidth memory (HBM) along with support for off-chip Intel Optane DC persistent memory. The top end will also support 112-Gb/s transceivers as well as PCI Express Gen 5.

The EMIB support is used to provide connections from the FPGA fabric to these interfaces, but it can also be used for custom tiles. Intel’s eASIC effort will allow companies to incorporate their tiles into custom Agilex FPGAs (Fig. 2). The eASIC is an Agilex FPGA with customer-supplied tiles linked to the system using EMIB. This provides the flexibility of an FPGA with many of the advantages of an ASIC, but with much lower startup costs. The approach can be used to integrate many chips into one, configurable platform.

Intel’s eASIC

2. Intel’s eASIC provides a bridge between FPGA solutions and custom ASICs.

The CXL support (Fig. 3) is one of the major advances for Intel’s FPGAs. Though it requires matching support in the host processor, it provides a common, cache-coherent, memory architecture that’s built on PCI PCIe. It essentially puts all CXL devices on the same level, allowing the FGPA to gain access to shared memory and peripherals.

Compute Express Link

3. Agilex supports the new Compute Express Link (CXL) standard for linking devices to host processors in a cache-coherent way.

CXL is a new platform and Agilex will be one of the first out there to include it. Intel will have matching support in a future Xeon family, at which point CXL becomes very interesting. From a programming point of view, there’s no difference between a processor and an FPGA working on the data in shared memory. It’s even possible that one instance of an application will use processor-based support while another employs an FPGA implementation. The operating system could transparently utilize what’s needed or available at the time.

Intel FPGAs are already used in the data center in the Alveo family, which employs PCIe interfaces. CXL also is built on PCIe, but it provides a lower-latency implementation because of the cache-coherent nature.

In addition, the Agilex FGPA fabric has been updated and optimized to handle new applications such as deep neural networks (DNNs) used in machine-learning (ML) applications. The configurable DSP now supports FP32, BFLOAT16, FP16, as well as INT8 through INT2. These are numeric formats being using in ML applications. It allows the DNN models to be optimized at each stage in an FPGA implementation without the overhead of using the FPGA fabric for all of the computation. The DSP block handles it more efficiently as long as it maps to the algorithm. Frameworks like the OpenVINO inference system for vision can take advantage of this accelerated hardware support.

The Agilex family comes in a number of versions (Fig. 4). The first one available is the F-Series, which has 58-Gb/s transceivers, PCIe Gen 4 support, DDR4 memory controllers, and an optional quad-core, 64-bit, Arm Cortex-A53 compute complex. The I-Series and M-Series kick the transceiver speed up to 112 Gb/s and support PCIe Gen 5. This is also where the CXL support comes into play. The M-Series is designed for compute-intensive applications. It adds support for DDR5 and Intel Optane DC. Furthermore, an HBM option puts large amounts of storage onto the system.

Agilex F-Series

4. The Agilex F-Series will be available first. The I-Series and the M-Series add CXL support, while the M-Series features HBM support.

The Agilex release coincides with new developer support. The Quartus Prime design tools deliver higher productivity through new workflows and a 30% improvement in job compile time. The tools also have a 15% memory utilization improvement. The tools include Intel’s VTune Amplifier and Intel Advisor support. The toolset handles all Intel FPGAs, including the new Agilex.

Intel expects the Agilex to be used in everything from 5G to data centers to embedded avionics.

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