Intel’s Stratix 10 FPGA family utilizes 14-nm transistor technology and heterogeneous 3D system-in-package (SiP) integration (Fig. 1) to combine different silicon technologies in the same package. It uses embedded multi-die interconnect bridge (EMIB) technology to link multiple die.
The platform targets applications like network function virtualization (NFV), data center acceleration, software defined radio and 5G wireless communication.
1. Intel’s Stratix 10 utilizes heterogeneous 3D system-in-package (SiP) integration with embedded multi-die interconnect bridge (EMIB) technology to link multiple die.
The new Stratix 10 SX family of systems-on-a-chip (SoCs) provides over one million logic elements (MLE) and integrates 1.5-GHz quad-core Arm Cortex-A53 MPCore support (Fig. 2). Versions are available with up to 5.5 MLE. The system employs Intel’s HyperFlex core fabric architecture to tie the components together. The SoC allows high-speed data-plane processing via the FPGA fabric, while the MPCore manages the control plane.
The HPS architecture implemented with the Stratix 10 incorporates a system memory management unit (SMMU) that enables hardware virtualization across the processor and FPGA domains. The family also supports a cache coherency unit (CCU) to provide one-way I/O cache coherency with the Cortex-A53 MPCore.
2. The Stratix 10 SX incorporates 1.5-GHz quad-core Arm Cortex-A53 MP support.
The FPGA fabric can include up to 10 TFLOPS of hardened, floating-point DSP blocks in addition to the embedded high-speed transceivers, hard memory controllers, and protocol intellectual-property (IP) controllers. The systems include a x8 PCI Express Gen 3 interface and three Ethernet MACs. There’s also 10/40G BaseKR- forward error correction (FEC) hardware support.
Additional hard logic includes AES-256/SHA-256 encryption/authentication support, a physically unclonable function (PUF), ECDSA 256/384 boot-code authentication, multi-factor key infrastructure with layered hierarchy for root of trust, and side-channel attack protection. A Secure Device Manager (SDM) handles updates of FPGA configuration code.
The Intel Quartus Prime Design software works with the DSP Builder for Intel FPGAs and Intel HLS Compiler for FPGA designs. The Intel SoC EDS, intended for software development, enables customers to utilize the Arm Development Studio 5 (DS-5) Intel SoC FPGA Edition to create and debug software applications. Developers can also take advantage of OpenCL support for the FPGA fabric using Intel’s OpenCL FPGA compiler technology.