Whether you’re using a leading-edge process node to manufacture a very large system-on-chip (SoC), or using an established node for automotive or Internet of Things (IoT) electronics, critical area analysis (CAA) and design-for-manufacturing (DFM) scoring are valuable techniques that can be used to improve the manufacturability, reliability, and (oh, yeah) the profitability of your products.
Design, Verification, and Manufacturing
The main responsibility of the foundry (the manufacturing side of the fabless semiconductor industry) is to achieve good die and wafer yields for their customers once the design is turned over to them for production. Foundry product engineers and production managers clearly understand the relationship between yield and profitability.
A low-yielding design requires more wafer starts to achieve volume goals, and uses up too much capacity, reducing foundry profits. What manufacturing staff usually don’t have is extensive expertise in the issues designers face in creating a design layout that not only complies with all of the required design rules, but is also optimized for power, performance, and area (PPA).
Likewise, on the design side, chip designers understand in detail the nuances and tradeoffs required to create a layout that meets both the manufacturing requirements and the product design specifications. However, they rarely have the opportunity to develop expertise in manufacturing issues that can diminish final yields or decrease performance, even though both of those outcomes reduce their profits. Without this knowledge, designers often apply DFM techniques in an opportunistic way simply because their methodology requires it, without truly understanding why or how these design changes help make the chip production more successful.