Electronic Design

10-Gbit/s Transceiver IC Delivers Jitter-Free Data

Secret ingredient in new IC is the key to meeting and beating all jitter specifications.

As Sonet, Ethernet, and other optical transmission standards push for higher data rates, jitter becomes one of the most critical design issues. Jitter has always been a nuisance. But at OC-48 and OC-192 Sonet speeds, and at 1- and 10-Gbit Ethernet speeds, it be-comes the limiting factor in many designs. Now, Silicon Laboratories of Austin, Texas, has developed an IC that greatly mitigates the jitter problem. It offers superior jitter performance of 5 mUI rms on the transmit clock line at an OC-192 rate of 10 Gbits/s (see "Jitter And Its Measurement," p. 50). The small but highly integrated 0.15-µm CMOS Si5600 SiPHY OC-192/STM-64 Sonet/SDH transceiver also features low power consumption.

Designed for serial communications at data rates from 9.9 to 10.7 Gbits/s, the device can be used in OC-192 applications that call for 15/14 forward error correction (FEC). It contains a 16:1 and 1:16 serializer/deserializer (SERDES), a clock and data recovery (CDR) circuit, a clock multiplier unit (CMU), and a limiting amplifier (Fig. 1). The device operates from 1.8 V over the −40°C to 85°C temperature range and dissipates an average of 1.2 W.

The chip is designed for use in almost any Sonet/SDH equipment, including routers, add/drop multiplexers, digital cross connects, optical transponder modules, and Sonet/SDH test equipment. It can also be employed in 10-Gbit Ethernet products.

The receiver part of the Si5600 gets its serial input from the optical diode and its transimpedance amplifier. It incorporates a sensitive limiting amplifier with ample gain, eliminating the need for other external amplifiers. The limiting amplifier fully saturates with as little as a 20-mV p-p differential input. Input signals exceeding 1 V p-p produce no performance degradation.

Moreover, the limiting amplifier incorporates a digital calibration algorithm that helps to cancel out amplifier offsets. It uses statistical averaging to remove noise that may degrade traditional calibration techniques. The amplifier also features loss-of-signal (—LOS) detection circuitry. The —LOS output is driven low when the input to the limiting amplifier goes below a desired preset value of about 10- to 50-mV p-p differential. This level is set by applying an external reference voltage of between 0.2 and 0.8 V to the LOSLVL pin. Built-in hysteresis of around 3 dB prevents unnecessary switching on the —LOS line. Tying the LOSLVL line high disables the —LOS line, forcing it high.

The CDR circuit rebuilds the clock from the serial NRZ input data. The recovered clock can then regenerate the data by sampling the limiting amplifier's output at the center of the NRZ bit time. The CDR also has a phase-adjustment feature that permits selecting the sampling instant used for data recovery. This sampling point can be moved over a ±45° range relative to the center of the incoming NRZ data period. This is useful in applications where the transmission medium introduces severe distortion, making data recovery difficult. Phase adjustment is made by applying a 0.2- to 0.8-V voltage to the PHASEADJ pin.

Next, the recovered data is converted into a 16-bit parallel output word by a 1:16 demultiplexer. The outputs are low-voltage differential signaling (LVDS), compliant to the OIF SFI-4 low-speed interface standard. The receive clock (RXCLK1 or RXCLK2) that multiplies the output data is derived by dividing the recovered line clock by 16.

Interestingly, the order of the receiver parallel outputs may be reversed. If the RXMSBSEL control line is tied low, the first bit received is placed on the RXDOUT0 output line, with the re-maining bits on the successively higher RXDOUT pins. But if the RXMSBSEL line is made high, the first bit received is sent to the RXDOUT15 output pin, with the following bits in reverse order.

A FIFO, a parallel-to-serial shift register, and the CMU make up the transmitter. The FIFO is eight 16-bit registers deep and provides a way to compensate for any phase delay or wander in the clock speeds of TXCLK16IN and TXCLK16OUT. The 16-bit LVDS input data is latched into the FIFO, then ultimately transferred to the shift register. From there it's transmitted serially at line speed under the control of the TXCLKOUT signal.

The shift register is set up to transmit MSB or LSB first. If TXMSBSEL is set low, then TXDIN0 transmits first. When TXMSBSEL is set high, TXDIN15 transmits first. This feature, like that in the receiver, can help in pc-board layout by simplifying bus routing in multichip, multiside board layouts.

The CMU takes the input reference clock and multiplies it by a factor of 16 or 64 to the final serial data rate. For a clock rate of 10.66 Gbits/s, the necessary rate for Sonet with FEC, the reference clock would be either 167 or 666 MHz. The TXCLKOUT signal operates the shift register.

Superior jitter performance is ensured by "a secret ingredient." The innovative circuit is a special digital PLL in the CMU. It uses a new architecture that incorporates a DSP loop filter. Silicon Labs calls it DSPLL. This patent-pending architecture greatly simplifies how optical transmission equipment is designed (Fig. 2).

In a standard analog PLL, the phase-frequency detector (PFD) compares the two inputs and develops an analog error signal, which an active RC low-pass network filters. Typically, the RC filter components are off chip as their integration is difficult and designers usually want to select values to optimize performance. These external components invariably pick up noise, which translates into jitter. Temperature changes, aging of these parts, and power-supply variations also influence jitter. While a ground shield around these components can minimize jitter, it doesn't eliminate it completely.

The DSPLL approach uses an analog PFD, but the analog error signal is sent to a special analog-to-digital converter. The digitized output is then filtered in a DSP low-pass filter. This process doesn't require any external components. The LC voltage-controlled oscillator (VCO) has a digital control input. The DSP algorithm generates a digital control value, which is used to adjust the frequency. With this ar-rangement, the VCO output frequency can be frozen by storing the digital control value. Plus, the DSPLL is totally insensitive to power-supply and temperature variations, as well as to any board noise.

The DSP filter is set up so that one of two loop bandwidths can be selected—wideband or narrowband. The BWSEL input line picks the bandwidth.

In the wideband mode, the bandwidth is 50 kHz. This bandwidth is implemented when a very low jitter source provides the reference clock. In this way, the DSPLL more closely tracks the reference source, providing the best possible jitter performance. On the other hand, the narrowband loop bandwidth is 12 kHz. This setting offers better filtering of the reference clock to help reduce jitter, and it permits operation with a noisier reference clock.

One benefit of the narrowband mode is that it enables the Si5600 to support Sonet/SDH-compliant loop-timed operations. This mode is chosen by the LPTM line made high. The transmit clock and the data timing are derived from the recovered clock output of the CDR. The recovered clock is divided by 16 and used as the reference source for the transmit CMU. What results is a transmit clock and data signal that's locked to the received data. The narrowband setting is recommended for this type of operation.

Built into the Si5600 are two loopback test modes that greatly facilitate diagnosis, measurement, and troubleshooting. The diagnostic loopback mode establishes an output from the serializer output to the deserializer input. This allows comparison of the low-speed parallel TXDIN data with the RXDIN parallel data. This mode is entered by making —DLBK low.

By making —LLBK low, the line loopback mode is entered. Doing so provides a loopback path from the high-speed serial receive input to the high-speed serial transmit output, allowing the comparison of the input clock and data to the transmitter data output.

To give designers maximum flexibility, Silicon Labs supplies a complete family of OC-192 and OC-48 parts. The receiver portion of the Si5600 is available as the Si5530. It contains the limiting amplifier, CDR, as well as 1:16 deserializer and related circuits. Also, the transmitter comes as the Si5540 with the built-in DSPLL CMU, the 16:1 serializer, FIFO, and associated circuits. Silicon Labs also recently announced its OC-48 transceiver ICs, which have similar architectures. The Si5100 is a transceiver with 16-bit buses, while the Si5110 has 4-bit buses.

A related chip using the DSPLL circuitry is the Si5364. It's a port card IC that generates four low-jitter clocks with outputs at either 19, 155, or 622 MHz with less than 1 ps of rms jitter. It also accommodates conversion to or from FEC clock frequencies. This chip provides Sonet Stratum 2, 3, 3E, and SMC compliance and features fully hitless switching.

Price & Availability
The Si5600 is sampling now with full production scheduled for the fourth quarter. It's priced at $555 each in 1000-unit quantities. The Si5530 and Si5540 are sampling now and run $270 each in 1000-unit quantities. The Si5100 and Si5110 sell for $157 and $148 each, respectively, at the 1000-unit level. And, the Si5364 is now available in production lots. In 1000-unit quantities, it costs $99.95.

Silicon Laboratories, 4635 Boston Lane, Austin, TX 78735; (877) 444-3032; fax (512) 416-9669; www.silabs.com.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.