The RXv2 32-bit RX CPU core pushes performance from 3.2 to 4.0 Coremark MHz or 2.0 DMIPS/MHz, with 300-MHz maximum frequency in 40 nm. Digital-signal-processing (DSP) and floating-point-unit (FPU) operations are performed simultaneously to boost signal-processing capability. Renesas’ RXv2 is backward-compatible with the RXv1 CPU core used in the RX family of 32-bit complex instruction-set computer (CISC) microcontrollers. RXv2 leverages RXv1’s architecture to improve computing performance, power efficiency, and high code efficiency via a dual-issue pipeline structure and advanced fetch unit (AFU, Note 1). RXv2 contains all RXv1 instruction sets, so RXv1 applications will be binary-compatible with RXv2. The new core features two dedicated 72-bit accumulators and a 1-cycle MAC instruction to enhance the DSP function, enabling the DSP to flexibly handle, perhaps, 32-bit fixed-point multiply-and-accumulate operation. Applications include factory automation, motor control, signal analysis, audio filtering, image processing, and connectivity.