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Electronic Design

3D Chip Design Crafts Imaging Subsystem On A Single Chip

For the past two decades, designers have attempted to create 3D circuits to reduce IC chip area, eliminate lengthy interconnections, and cut chip counts. The latest attempt by the Massachusetts Institute of Technology and 3D-IC, both of Lexington, Mass., combines a back-illuminated 64- by 64-pixel image sensor array with ring oscillators and fully parallel analog-to-digital conversion to deliver a digital image output to a host system.

To create the 3D circuit, the active layers are fabricated using silicon-on-insulator wafers bonded together after the circuits in each wafer are fabricated. On one SOI wafer, researchers fabricate the photodiode imaging array. On a second wafer, they craft the analog-to-digital converters (ADCs). The wafers are then bonded together, stacking the multiple circuit layers. The stacking also permits the unrestricted placement of dense 3D vias, and that lets designers easily interconnect the multiple layers.

Most previous attempts at implementing 3D circuits used hard-to-fabricate recrystallized silicon. With the bonded-wafer approach, designers can separately optimize each circuit function, maximizing performance.

Built from inverter strings, the ring oscillators are half fabricated in each wafer. A CMOS inverter in one wafer is connected to the next inverter in the other wafer when the wafers are bonded. The imaging array is fabricated in a 10-µm epitaxial layer on a 0.3-µm bonded and etched-back SOI layer. The SOI layer sits on top of a 1.0-µm buried-oxide layer. The thickness of the epitaxial layer is selected to yield good optical performance in the visible and near-infrared spectrum.

The ADCs are fabricated in a 1.0-µm thick SOI layer that also sits on top of a 1.0-µm thick buried-oxide layer. The circuits in both wafers are fabricated with a two-level metal 0.8-µm CMOS process that enables operation at 5 V. Prior to the circuit fabrication, silicon trenches are etched through the SOI layer of the ADC wafer. Those trenches are then filled with deposited oxide to form channels through which 3D vias could be etched to interconnect the active layers on the two wafers.

After each wafer is fabricated, the one containing the ADC is inverted, aligned to the imager wafer using an infrared aligner, and bonded to the imager wafer using a 3-µm thick adhesive layer. The bulk silicon is then etched from the back of the ADC wafer, exposing the buried-oxide layer, which also serves as an etch-stop for the etch process. The result is a thin, uniform, active layer on top of the imager wafer.

Next, shallow 3D vias are etched through the exposed buried-oxide layer, the trench-oxide region, and the deposited-oxide layer on the surface of the ADC wafer (between the original wafer surface and the first level of metal). As a result, the vias expose the bottom side of the metal pads on the first metal layer of the ADC wafer and allow connections to the metal layer.

A second set of deep vias also is defined. These vias are etched entirely through the ADC wafer and the adhesive to expose the metal pads on the second metal layer of the imager wafer. All the vias are 6.0-µm2 and are nominally 2.7- and 7.5-µm deep, for the shallow and deep vias, respectively. A sputtering process is then used to deposit an aluminum alloy on the exposed buried-oxide layer. This layer is then patterned to connect the metal pads of the two wafers. The dual-wafer assembly is then inverted and bonded to an oxidized silicon wafer for mechanical support.

Next, the exposed back bulk-silicon portion of the imager wafer is removed with etching to expose the epitaxial layer. This lets the light easily reach the photodiode imaging array through the exposed epitaxial layer. Additional bonding pads are then defined, and the proper contact vias are opened by another etch step. Then, metal is deposited and patterned. The final step involves dicing the wafer and packaging the individual chips.

The resulting imaging array can respond to a wide range (over 100 dB) of incident-light intensities. Power consumption, both static and dynamic, is also minimized—just 60 nW per pixel with a 3-V supply under average room-lighting conditions. In the test chip the researchers fabricated, several bad pixels exhibited a high local dark current. A few other bad pixels had excessive leakage current. But overall, the researchers had very good success with the 3D via chains and the over 4000 deep and shallow vias that had to be fabricated.

The next project will be to employ three levels of metal interconnect and a 0.25-µm, fully depleted SOI technology that will allow the stacking of three or more circuit layers. Those layers will be interconnected with 3D vias whose size, pitch, and resistance will be decreased by replacing the adhesive process with a low-temperature oxide bonding scheme and tungsten plugs to fill the high-aspect-ratio vias.

This research was jointly detailed in paper 17.1 at this month's IEEE International Solid-State Circuits Conference, San Francisco. For more details, contact presenter Lisa McIlrath at [email protected]

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