With system, software, and semiconductor design activities converging, increased challenges have stood in the way of creating complex systems-on-a-chip (SoCs). More than just a trend, interoperability has become a necessity— with subsequent standards following suit. To provide a single organization focused on electronic-design-automation (EDA) and intellectual-property (IP) standards, Accellera Systems Initiative— an independent nonprofit organization focused on the creation and adoption of EDA and IP standards— has acquired the assets of the Open Core Protocol International Partnership (OCP-IP).
The transfer of assets includes the current OCP 3.0 standard and supporting infrastructure, which facilitates the reuse of IP blocks used in the design of semiconductor products. OCP 3.0 is a non-proprietary, openly licensed, core-centric protocol. It describes the system-level integration requirements of IP cores while unifying inter-core communications. The standard eliminates the need to repeatedly define, verify, document, and support proprietary interface protocols while adapting to support new core capabilities. At the same time, it vows to limit test-suite modifications for core upgrades.
The protocol serves three main functions. The first is to achieve the goal of IP design reuse—OCP 3.0 transforms IP cores, making them independent of the architecture and design of the systems in which they are used. It also optimizes the die area by configuring it into the OCP interfaces that are needed by the communicating cores. Finally, OCP 3.0 simplifies system verification and testing by providing a firm boundary around each IP core, which can be observed, controlled, and validated.
Any on-chip interconnect can be interfaced to OCP 3.0 for a variety of on-chip communications including dedicated peer-to-peer, simple slave-only applications, and high-performance, latency-sensitive, multi-threaded applications. According to Accellera, the protocol supports high-performance data-transfer models and can support higher-complexity SoC communication models with the use of thread identifiers, which manage the out-of-order completion of multiple concurrent transfer sequencers. Version 3.0 includes added features, such as coherence extensions, updated semantics for the write-response-enable, an advanced high-speed profile, and support for new sideband signals to control the connection state of the interface based upon the input of both master and slave.
Acellera aims to leverage the OCP’s standards and member base with its current portfolio, which serves the electronic-design community by increasing productivity and reducing development costs. This move follows the mergers and acquisitions of the Open SystemC Initiative (OSCI), Virtual Sockets Interface Alliance (VSIA), and the SPIRIT Consortium. An FAQ has been provided for members at OCP-IP or Accellera as to how the acquisition will affect their status.
Information used in this article was gathered from the Open Core Protocol 3.0 Specification.