As the number of high-performance on-chip peripheral functions supporting a system-on-a-chip (SoC) solution increases, bus traffic overwhelms the standard on-chip buses linking the CPU core to the functions. And unlike current conventional buses that support single-issue CPUs (500 MHz or slower), few defined bus architectures are optimized to operate with CPUs that can clock at 1-GHz and faster.
That dilemma led PMC-Sierra to develop the Fast Device Bus (FDB). This tiered bus architecture with a generic device interface leverages 1-GHz dual-issue superscalar CPUs (see the figure). The FDB's unique two-stage central arbiter grants a device request to the main bus only if the target of the request can accept it.
Each device is permitted a fixed number of requests to the central arbiter. An innovative flow-control, credit-based arbitration scheme in the central arbiter also recognizes device request priority and guarantees "fair access" to all target devices, including high-contention targets. With this central arbitration scheme, use of the main bus can be scheduled more efficiently without incurring wasted cycles for main bus "retries" and "not acknowledge" responses most other standard bus architectures require.
The first SoC device to implement the FDB, the RM9150MR, is a highly integrated solution that includes the E9000 MIPS processor core, dual 16-kbyte instruction and data caches, and a unified 256-kbyte level 2 cache. The FDB supports the CPU. Two 32-bit PCI ports, two 10/100/1000 Ethernet MACs, a 200-MHz, 64-bit DDR1/DDR2 SDRAM controller, a 600-MHz DDR 8-bit HyperTransport interface, and still other peripherals are tied into the FDB.
The GDI enables very modular SoC designs in which blocks of IP can be easily added or subtracted. The FDB is a 500-MHz, multiple-master shared bus that uses a 128-bit wide multiplexed address and data path. The chip's CPU core will offer speed grades from 600 MHz to 1 GHz, but the first implementation will run at 600 MHz and cost about $85 in moderate lots.