Electronic Design

Build A Zero-Power Switch Supervisor

A recent project requirement specified the need for a special indicator to show whether a security switch was used during the time the system was powered off. Because our system has a real-time clock (RTC) with a 3-V battery, we needed to run the circuit from this battery without significantly draining it. The specification called for a battery life of at least five years at the nominal 200 nA of the RTC.

The basic approaches to this type of low-power design requirement are: a) use CMOS; b) try to keep all signals stable since switching means charging/discharging of capacitors, which consumes battery power; c) eliminate any static current through pull-up resistors or similar; or d) apply battery power only to the absolutely necessary components.

The circuit’s core consists of an OR gate IC1, in a single-gate package (see the figure). This logic gate is powered by the battery and will attempt to maintain a capacitor at its actual logic level. Typically, the capacitor is charged up to VBAT. If SWITCH is grounded (i.e., the security door is opened), the capacitor is discharged and the logic level drops to a logic low. The circuit will actually work without C1 (using only the gate capacitance of the gate), although this would make it very susceptible false operation due to noise.

During normal (power-on) conditions of the machine, the microcontroller monitors the —STATE output. The Q1/R3 combination isolates the battery-powered OR gate and the input of the microcontroller I/O pin. Without it, the input protection diode (to 5 V) of the microcontroller would cause increased current at the 3-V OR gate’s output. This isn’t a problem on the input side of the gate, since the inputs of the gate accept up to 5.5 V independent of the gate’s supply voltage.

If the microcontroller detects that the capacitor is discharged, it charges the capacitor again by setting the second input of the OR gate to a logic high level. If the switch is open, the capacitor will reach 2.1 V (which is read as a logic high by the gate) after about ln(3)*R1*C1 seconds. The SET signal may then be reset to a logic low. If the switch remains closed, the capacitor will remain at a logic low level. This can be detected by the unchanged logic level of —STATE. To reduce current consumption, the microcontroller only charges the capacitor once every second, yielding an average current of C1*VBAT*(frequency). For this design, the average current is about 3 nA.

Special care must be taken to ensure that SET isn’t pulsed during power on. That’s because the logic will be set to high, thus losing the state of the switch during the poweroff time. If this is unavoidable, a lowpass filter can be added at the input, or a slow optocoupler can be used.

Actual measurements resulted in a standby current consumption of about 0.4 nA in the low state and about 0.7 nA in the high state.

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