The CoverMeter code coverage tool extends the power of Verilog simulation to confirm that all portions of a design have been fully exercised, assuring design quality while reducing verification effort. The tool works with simulation to determine which portions of the design have not been exercised by test cases and require further attention. Armed with this information, designers can then quickly develop new test cases to exercise only the untested portions of the design.The tool provides for line coverage, which breaks lines in source code into individual statements with probe points so that coverage information can be provided specific to separate logical entities. It also provides condition coverage and a User-Expressions tool to support investigation of the behaviors of interacting state machines.
Company: SYNOPSYS INC.
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