Electronic Design

Consolidation Looms In Verification

The year 2003 will see design teams shift from IC implementation to functional verification. The actual kickoff for this switch was at DAC 2002 in New Orleans, where Synopsys introduced an intelligent test bench offering along with Release 7.0 of its mixed-language register-transfer-level (RTL) simulator. Cadence's intelligent test bench, which has been on the market for a few years now, recorded $13 million in sales for 2001.

Two things became evident with the Synopsys announcement at DAC. For one, standalone Verilog or VHDL simulators have been relegated to the low-cost lower mainstream and late-adopter end of the EDA tool market. Also, as expected, the intelligent test bench vendors fully intend to offer a bundled solution. There are obvious reasons for this, most of which are marketing driven.

So just what is an "intelligent test bench?" Basically, it's the automation of the RTL verification flow. It is the cockpit, as Cadence calls it, which partitions the design into verification blocks, then drives the various verification tools to ensure proper verification coverage. A simple example would be the use of a Verilog simulator for a Verilog block and a VHDL simulator for a VHDL block, in essence automating what's done manually today. This, of course, saves engineering time. The intelligent test bench will also prevent the repetitive verification of a block while other blocks are left unverified, conserving even more valuable engineering time. The intelligent test bench isn't the technical challenge that the IC implementation tool set has been. However, in a world where functional verification is beginning to take as much time as the design portion of the implementation flow, it will dramatically affect the time and cost within the design cycle.

What will be the marketing impact? At the start of this year, 81 (count 'em, 81) functional verification vendors existed. Now there are between 11 and 18 different functional verification tools on the market, depending on how you want to count them. In the best-case scenario of an evenly divided-up market with different players in each subsegment, there is room for 36 vendors. The bad news is that the intelligent test bench vendors see no need for an evenly divided-up market. You'll recall that I mentioned Synopsys and its "bundled" solution. One needn't be a brain surgeon to predict a major consolidation in the functional verification space. In fact, it has begun already. So how many will be left standing? I'd say less than a dozen will survive.

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