Electronic Design

Correct-By-Construction Layout Generation And Modification

Physical design verification software typically identifies faults in physical layouts by finding design-rule-check (DRC) violations and layout-versus-schematic (LVS) mismatches after layout is complete. So-called "correct-by-construction" layout generation is a method for generating and modifying polygonal features during the layout construction process so that the layout satisfies both design-rule constraints and connectivity requirements. Whether the design is flat or hierarchical, correct-by-construction polygon processing techniques can be used to verify that construction is proceeding correctly.

Developing formal approaches to a correct-by-construction methodology allows physical verification software to move from mere fault finding into physical design generation and modification, expanding the capabilities and usefulness of existing software. Beyond layout accuracy, however, a correct-by-construction approach can be used with polygon processing techniques to perform automated layout construction and improvement.

This article describes the use of a correct-by-construction methodology for creating a ground plane and its associated power/ground grids. The power features are added onto an existing layout using a TCL scripting language, and the generation and mounting tasks are managed with a Perl driver. For this project, we combined Mentor Graphics’ Calibre nmDRC (to provide the polygon management) and the TCL and advanced merge features of Mentor Graphics’ Calibre DESIGNrev (to provide the database handling), supplemented with Perl (for general-purpose data and string processing). Calibre nmDRC and Calibre DESIGNrev combine to provide the complementary polygon processing capabilities required by a correct-by-construction methodology (see "About Polygon Processing Engines").

Correct-By-Construction Techniques
Broadly speaking, there are two types of layout generation or modification: flat and hierarchical. In flat layouts, database manipulation is not needed. However, polygon processing features are exercised to deliver correct-by-construction flat layout cells. Whether the layout is a very complicated ground/power plane, or something as simple as a p-cell, the goal is always to ensure that the layout is constructed correctly, yet can be easily reconfigured with a different set of starting parameters.

In the case of hierarchical construction, intricate database manipulation often takes center stage. Why? Because the generated or modified layout must be DRC/LVS correct, and its addition to the existing layout should not break the structural configurations of the leaf cells or the existing hierarchies. Polygon management alone cannot manage all of these stringent requirements, which is why we use a TCL with advanced geometry-sensitive layout database manipulation features, such as cell selective reference expansion, iterative cell reference deletion, etc. For example, a selective reference expansion scheme avoids breaking leaf-cell structures during a metal subtypes change procedure.

Flat Layout Construction: The Ground Plane Project
The ground plane facilitates the supply of low IR-drop electrical ground to the active devices (transistors) from a perforated metallic plane. This plane is normally built with a metal layer located above the routing metal layers for the subcells, typically Metal5 or Metal6. An IR analysis verifies IR-drop compliance.

The ground plane also serves as a capacitive shield for the signal lines and is perforated with staggered arrays of cheesing holes to comply with metal density requirements (Fig. 1). Staggering the perforations helps prevent current channeling and formation of inductive loops, and the holes break up the wide metal regions requiring wider design rule spacings. In addition to the cheesing perforations, other holes must be created by the program to let VDD, clock, and signal nets pass through.

Signal routing (using ground plane metal) that eventually passes through the ground plane’s signal-connection islands is normally restricted to available channels that are design-rule-safe with respect to the periodic VDD, VSS, and clock lines. In a correct-by-construction scenario, the ground plane with the holes and islands is connected to VSS lines below and above the ground plane, using the maximum number of vias that can be placed without breaking the design rules. Even the VDD and clock lines below and above the plane are connected through the connection islands. The periodic placement of the VDD, VSS, and clock lines or straps, and all via placements, is also controlled by the ground-plane-generating program.

In some cases, there may be special electrical requirements. For example, if the pre-existing routing connections are placed outside the restricted channels, or there are pre-existing VDD, VSS, and clock lines in non-periodic locations, the correct-by-construction program should bypass those features on the layout, and place the new straps in a DRC-correct way.

At least some of these complexities can be handled by the generated ground plane (Fig. 2). Connection holes are created for the signals and VDD lines. Via islands are also created for the VDD connections. The maximal via filling for VSS straps is put into effect. Figure 2 also demonstrates the automated interruption of program-generated vertical VDD/VSS straps from above to accommodate off-channel routings and straps below.

A typical ground-plane-generation techfile is built up in a number of correct-by-construction development steps. The following are correct-by-construction steps for developing a plane (Metal5) and straps (Metal6 – Metal9):

  1. Create the staggered perforations.
  2. Create Metal6 VSS and VDD straps.
  3. Subtract existing Metal6 materials in a DRC-correct way.
  4. Create DRC correct exclusions for existing Via4 – Via8.
  5. Create DRC correct exclusions for existing Metal5 materials.
  6. Create the Metal6 – Metal4 VDD connects.
  7. Create exclusions for existing and new Signal/Clock/VDD connects.
  8. Adjust the set of staggered perforations with the exclusions.
  9. Create DRC-correct ground plane and reduce wide metal regions.
  10. Create DRC-correct vias to the Metal4 VSS straps.
  11. Create DRC-correct vias to the Metal6 VSS straps.
  12. Create Metal7 VSS and VDD straps.
  13. Subtract existing Metal7 materials in a DRC-correct way.
  14. Create Metal8 VSS and VDD straps.
  15. Subtract existing Metal8 materials in a DRC-correct way.
  16. Create Metal9 VSS and VDD straps.
  17. Subtract existing Metal9 materials in a DRC-correct way.
  18. Create DRC correct maximal Via6-Via8, obeying existing exclusions.
  19. Check all vias (existing and created) for stress vias.
  20. Delete any stress vias from the set of generated vias.
  21. Output all generated metals and vias into a flat GDS database.

If this GDS database is named cell_name_ground_plane.gds (derived from the original cell database cell_name.gds), the ground plane can be mounted on the cell using TCL code such as:

set L1 \[layout create "cell_name.gds"\]
set L2 \[layout create "cell_name_gnd_plane_only.gds"\]
$L2 cellname cell_name cell_name_gnd
$L1 import layout $L2 FALSE append
$L1 create ref cell_name cell_name_gnd 0 -0.215 0 0 1
$L1 gdsout "cell_name_with_gnd_plane.gds"

Once generation and mounting are completed, the final database (cell_name_with_gnd_plane.gds) is tested for DRC, ERC, and LVS correctness of construction.

A correct-by-construction generation must also meet IR-drop requirements and mask-printability requirements to be viable. To ensure compliance with these requirements, the generation should be modular and driven by a simple set of perforations and straps periodicity (pitch/width/spacing) parameters. Normally, this is accomplished by driving the generation from a file of variables, where you simply change the variables to generate a slightly different plane for better compliance. This ground-plane parameters file makes the generation programmable.

Correct-By-Construction Considerations
The important emphasis on correct-by-construction in the generation process is to ensure that each of the 21 steps in the generation techfile is DRC- and LVS-correct. In addition, the proper sequencing of the steps is important for a clean design. Continuously check and correct for slivers, narrow necks, wide metal regions, improper via enclosures, unwanted intersections, or proximity with existing materials, etc. At the end of the generation process, only the more complicated metal stress via errors remains. Devote a section of the generation techfile to finding those errors, and then remove all generated vias that have stress via errors. Since via generation is maximized, even for wrong-way metals (for example, a horizontal metal strap in Metal6 where the routing direction is vertical), appropriate application of the rectangles construct ensures that not too many vias are lost in stress vias correction.

The parameters-driven staggered perforations scheme should first be tested for maximum metal density violations. If the DRC-correct perforations are too small or too far apart, they can lead to maximum metal density violations or too many wide metal regions. Apply proactive OPC checking to avoid mask-printability issues later on. These considerations drive the selection of the size, spacing, and offset of the ground-plane perforations defined in the ground-plane parameters file. The stagger is not applied to the peripheral columns and rows of the plane (Fig. 1, again). This is intentional to ensure smooth transitions from the plane of one layout sub-block to that of another, even when some blocks may be rotated before placement. Sub-block sizes are restricted to integral multiples of standard-cell sizes. This restriction ensures continuity of straps and ground plane from one block to another.

The power/ground metal strap widths and pitches are pre-defined in the ground-plane parameters file. Select these widths and pitches based on standard-cell VDD/VSS pitches, as well as IR-drop considerations. Once the straps pitch grid is selected, compute the allowable DRC-correct routing channels for any block, and use that information proactively in sub-blocks routing and implementation to ensure that the ground-plane generation does not conflict too much with existing routing.

Hierarchical Layout Correction: Selective Reference Expansion
The ground plane project is an example of intricate flat construction, where the correctness of construction applies only in the flat sense. However, designers often must deal with hierarchical layout, such as changing some features of metallization based on net identities of metals in a hierarchical layout.

One good example is metals subtypes correction. In complex custom designs, designers often deal with multiple power-supply voltages, clock nets, ground supply, and signal nets, all on any particular metal layer. In such situations, it’s often advantageous to employ different layout layers for nets used for different purposes.

For instance, VDD, VDDX, VDDY, VSS, CLK, and Signal metals could use different metal subtypes in layout. In this scheme, for any particular metal layer (e.g., Metal4), we have subtypes such as VDD04, VDDX04, VDDY04, VSS04, CLK04, and Sig04 represented by different data layers in the layout. This scheme not only helps visualize the different nets of a complex layout, it also helps in developing layout debug software, such as a shorts isolator program. All of the different subtypes with a 04 suffix are processed as a single metal layer (Metal4 in this case) at the mask-making stage and for physical design verification purposes.

However, layout designs originating in different design groups of an organization often do not strictly adhere to the metal subtyping mentioned above. Sometimes, layout blocks are designed with the wrong metal subtypes—for example, VSS04 used in parts of VDD net in Metal4, or Sig04 used for VSS net, etc. A correct-by-construction solution can be used to automatically detect wrong subtypes and replace them with proper subtypes. This solution requires that the layout block to be corrected is properly texted and LVS-correct to start. In principle, this is a straightforward process to identify the wrong metal subtypes with the NET construct. For instance,

BAD_Sig04_VDD = Sig04 NET "VDD"
identifies the Sig04 metal subtype used wrongly on " VDD" net. Similarly, we can get wrong Sig04 on nets other than signal nets, and finally,
GOOD_Sig04 = ((((Sig04 NOT BAD_Sig04_VDD) NOT BAD_Sig04_VSS)

This way, BAD_ and GOOD_ of all metal subtypes are computed for all metal layers. They are output into a GDS database, with BAD_s assigned a layer number that maps to the layer number of the net where the error was detected. For example, if the layer number of VDD04 in the original layout was 64, BAD_Sig04_VDD is output into layer number 5064 from the techfile. Bumping up the value of the layer number by 5000 provides a convenient value well above the maximum layer number used in the original database.

In addition, the GOOD_s are output to a layer number that maps to the layer number of the proper subtype. For example, if Sig04 in the original database had a layer number of 100, the GOOD_Sig04 is output to 5100 from the techfile. For example,

BAD_Sig04_VDD \{COPY BAD_Sig04_VDD\}
GOOD_Sig04 \{COPY GOOD_Sig04\}
DRC CHECK MAP BAD_Sig04_VDD 5064 //If VDD04 is 64 in input
DRC CHECK MAP GOOD_Sig04 5100 //If Sig04 is 100 in input

and so on for other subtypes and metal layers.

If HCELL cell_1 cell_1 through HCELL cell_n cell_n is used for all cells in the database in this DRC techfile, the data should be output in a proper hierarchical distribution of the cells and subcells. Simple TCL code can then incorporate the data from the run into the original database. If the original database is testcase.gds, the output of the metal subtypes identifying techfile can be testcase _metal_diag.gds. The TCL code that handles layers 5064 and 5100 looks like this:

set L1 \[layout create "testcase.gds"\]
set L2 \[ layout create "testcase_metal_diag.gds"\]
$L1 import layout $L2 FALSE append

if \[$L1 exists layer 5100\]\{
$L1 delete layer 100
$L1 COPY 5100 100
$L1 delete layer 5100

if \[$L1 exists layer 5064\]\{
$L1 COPY 5064 64
$L1 delete layer 5064

$L1 gdsout "testcase_with_new_metal.gds"

This code simply maps the bumped-up layers back to the original layer. This way, the entire database is corrected with the results of the diagnostic techfile, for all subtypes in all metal layers.

Selective Reference Expansion
Some issues still must be resolved with the above procedure. For cells with multiple instances, where a particular metal subtype occurs on different nets in different instances, the above procedure corrects that metal differently in each instance and moves the corrected metal subtype one level up, leaving the cell saved without the metal. This means the leaf cell or subcell structure is broken in the corrected database with respect to the original database. This issue of "conflictingly connected" instances can be addressed in two ways:

  1. Do not correct those cells in the database.
  2. Selectively expand only those instances where the metal subtype is on a wrong net.

The second method is more interesting because it involves a more intricate application of TCL. In our case, we have numerous instances of via cells used in the layout. All of these via cells are in the shape of a cross between signal metals and a via sandwiched at the center. In one example, a Via01 cell consists of a crossing between Sig01 and Sig02 with a V01 at the center (Fig. 3).

The Via01 cell shown above is used freely for signal nets, as well as VDD, VSS, or any other special nets, so it is an example of a conflictingly connected cell. If we follow the procedure discussed earlier, the cell will be broken up and saved in the final corrected database with just the V01 in it. That is, the leaf cell structure would be broken.

A procedure is needed to identify those via cells that are connected to special (non-signal) nets and to expand (flatten) their contents to add to the cell where they have been instantiated. If the metal subtypes correction procedure discussed above is applied on the database with selectively expanded via cells, the correction no longer breaks the via leaf cells.

The selective expansion procedure needs to be perfect, because if even a single via cell on a special net (non-signal net) remains unexpanded, the subsequent metal subtypes correction will break the leaf cell. To accomplish this, a two-step procedure involving a techfile identifies the BAD_Via0x (where "x" stands for Via level) cell extents that interact with the various "special" nets (VDD, VSS, CLK, VDDX, VDDY).

However, this is not enough because the software works on polygons and will report only one BAD_Via0x cell for multiple coincident (in space) placements in the hierarchical direction. If it reports a BAD_Via0x in such situations, the BAD_Via0x will be associated with only one of the parent cells where the Via cell is instantiated. If that BAD_Via0x polygon is used in subsequent TCL as the sole basis for selecting Via0x instances for expansion, the other Via0x cell that was sitting on top of it and instantiated from another parent cell would remain unexpanded.

To circumvent this situation, we need the BAD_Via0x as the basis of selective expansion (because it takes care of most selections in a correct way), as well as the special net metals surrounding an expansion candidate. This is accomplished in TCL by reading in the original layout database, and calculating the OR (Boolean function) of the special subtypes read in for each layer. Call it "spnets_or_0x," where "x" stands for the metal level. In contrast to the BAD_Via0x entities obtained with the run, spnets_or_0x is not collapsed to one of the multiple cells when coincident placements occur.

However, because a Via0x cell can interact with a "spnets_or_0x" entity or with a "spnets_or_0x+1" entity, a Boolean OR of "spnets_or_0x" and "spnets_or_0x+1" forms the geometric basis of expansion. Combine the "net" basis of expansion, namely, BAD_Via0x, and the geometric basis of expansion into a single basis of expansion, ALL_ BAD_Via0x, where:

ALL_ BAD_Via0x = BAD_Via0x OR (spnets_or_0x OR spnets_or_0x+1)

In the TCL code, first form this basis of selective expansion for all metal and via layers after reading in the original database, and the results of the run. Then, for each cell, look for references that match in name with Via0x cells. If the match is found, create a small polygon at the center of the matched reference. Then perform a Boolean AND function for this polygon with the ALL_ BAD_Via0x entity. If the intersection is positive, the Via0x cell is expanded, and its contents added to the parent cell.

Did we miss anything? What if the geometric basis of expansion obtained from spnets_or_0x OR spnets_or_0x+1 failed to pick up an expandable reference because Sig0x metal was incorrectly used on a special net near a Via cell? This situation can be avoided by also obtaining the entities such as BAD_Sig0x_ from the pre-run, along with the BAD_Via0x extents. The BAD_Sig0x_ entities can be recognized from the wrong metals diagnostic in the techfile, so simply add that feature to this selective expansion pre-run techfile to put out those entities as well as BAD_Via0x. Then, in the TCL code, add these new entities to the selection basis:

ALL_ BAD_Via0x_new
= ALL_BAD_Via0x OR (BAD_Sig0x OR BAD_Sig0x+1)
where the BAD_Sig0x is the Boolean OR of all the separate BAD_Sig0x_ entities ( BAD_Sig0x_VDD, BAD_Sig0x_VSS, and so on).

Once done with the selective expansion, create an intermediate database (GDS) with selectively expanded via cells. This intermediate database becomes the input to the metal subtypes correction procedure. Ensure the hierarchical correctness of the process through a cell-by-cell XOR of the corrected database with respect to the original database. The XOR should be null for all layers, as well as for the Boolean OR of the metal subtypes.

Consider an example of the correction of a leaf cell (Fig. 4). On the left is the metallization of the cell before the subtypes correction was applied, and on the right is the same cell after correction. Along with the subtypes correction, there is an effect of metals merging that cleans up the layout to some extent. For example, the Sig01 (green) metal on the left has pieces put together to form clean single polygons on the right. This is an added benefit of the correction process.

This project explored some of the intricacies involved in flat and hierarchical construction. For the tasks involved in flat construction, geometric design rule issues are of primary concern. For hierarchical construction, layout database issues are of greater importance. Exploiting the programmability of existing EDA software can create a generalized correct-by-construction tool for all types of automated layout generation and correction.

I would like to sincerely acknowledge the contributions of James Paris of Mentor Graphics in helping develop TCL code for instance-specific layout editing using Calibre DesignREV generic commands. I would also like to acknowledge Lata Valluri, Gene Forte, and very specially Shelly Stalnaker of Mentor Graphics for taking interest in this work.

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