Electronic Design

Design PCI Express In Embedded Design FAQs

Q: What is PCI Express?
A: PCI Express is a scalable, high-speed, point-to-point serial interface designed to replace PCI. Also known as PCIe, it features power management, quality of service (QoS), hot-swap support, error handling, and improved data integrity. It supports chip-to-chip connectivity, backplanes, and chassis-to-chassis connections as well. PCI-SIG standards define a range of connectors, cabling, and form factors.

Q: What are some PCI Express form factors?
A: The PCI Express card is found in most desktop PCs. The smaller PCI Express Mini Card and Express Card find homes in mobile devices, while the ExpressModule targets servers. Several organizations define additional form factors using PCI Express like the SFF-SIG’s SUMIT.

Q: How compatible are PCI and PCI Express?
A: PCI Express is functionally compatible with PCI from a software perspective. The two differ significantly in physical implementation because PCI is a parallel bus supporting multiple connections. It is relatively easy to connect PCI devices to PCI Express systems via bridge chips.

Q: How does PCI Express work?
A: PCI Express can support a single host connected to a root complex (Fig. 1). PCI Express connections can be expanded using a PCI Express switch. It can be linked to PCI buses using a bridge chip.

Q: Are there different PCI Express versions?
A: PCI-SIG is moving PCI Express into its third generation. Each specification is backward-compatible, allowing newer devices to meet the requirements of earlier standards.

Q: What goes over a PCI Express link?
A: The first two generations of PCI Express use 8b/10b encoding for the serial data. Gen 3 hits 8 Gtransfers/s with more efficient 128b/130b encoding. Each lane is full duplex, and its signaling is independent in multiple lane links. Packets handle all information being exchanged over a link.

Q: How does PCI Express handle interrupts and direct memory access (DMA)?
A: Interrupts and other sideband communication such as power management are simply packets with header and data information that is specific to the type of communication. DMA is simply packet communication between nodes.

Q: Does PCI Express scale?
A: More bandwidth is attainable in two fashions: higher speed and more lanes. Each successive generation of PCI Express has increased the clock rate. All provide multilane capability supporting x1, x2, x4, x8, x16, and x32 connections. The x16 lines are most common with graphics processing units (GPUs) and redundant array of independent disks (RAID) storage. The x1 and x4 connectors are common on PCs.

Q: Can a PCI Express system support multiple hosts?
A: PCI started as a single-root architecture and is usually sufficient for embedded PCI Express applications. PCI Express does bring new concepts to the table including reverse bridging, multi-root complex, and I/O virtualization (IOV).

Q: How does PCI Express fit into embedded applications?
A: PCI Express x4, x8, and x16 connections are common in PCs and servers, but x1 links are often more than adequate for handling embedded devices. Express Cards for laptops utilize a x1 link. High-end microcontrollers often have x16 connections to address high-bandwidth applications. Lately, a number of lower-end microcontrollers have become available with a small number of x1 links, making them ideal for embedded applications requiring less bandwidth.

Q: Can microcontrollers be PCI Express devices?
A: Yes. A number of microcontrollers have interfaces that can operate in either mode. Many PCI Express peripheral devices incorporate microcontrollers. Some microcontrollers can act as a bridge providing both types of PCI Express interfaces, such as a SAS RAID controller (Fig. 2).

Q: What is I/O virtualization?
A: A physical PCI Express device that supports IOV has multiple logical devices. It can present a logical device to a virtual machine on the host. From the virtual machine’s standpoint, the environment looks like a single-root PCI Express system with a real, dedicated device.

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