The gossip: Analog and digital will soon battle for control of power-supply regulation. The reality: When it comes to feedback-loop control, both approaches seem to happily coexist. (See "True Digital," p. 46, and "Looks Like Analog, Designs Like Digital," p. 48.)
Indeed, many vendors offer a choice. Some of digital control's initial programmability advantages are now available even in controllers and regulators that use analog feedback. Still, digital power has some appeal.
"Power supplies have become a part of the overall system, and they're expected to handle power management," says Mikhail Guz, Power-One's director of strategic marketing and applications. "That last point is particularly important as more and more system engineers want to be able to talk to the power supply in real time for monitoring and diagnostics." Many power-management engineers agree.
"An engineer can use a single digital product in many different modes and applications," Guz continues. "They can relatively easily implement adaptive control and nonlinear control algorithms. Unlike analog, digital controllers are not subject to component tolerances and aging effects. Moreover, most of the digital control loop is built on CMOS processes that scale much more readily than analog processes, leading to cost savings in future digital generations."
WHAT'S IT ALL ABOUT?
To set the parameters for discussion, we're talking about pulse-width-modulated (PWM), pulse-density-modulated (PDM), and pulse-frequency-modulated (PFM) switching regulator and controller ICs. Some integrate drivers for the transistor or transistors that do the actual switching. Others don't. Some even include the switching FETs, if they supply modest loads. Consequently, the digital-versus-analog issue depends on how the regulator's control loop is closed.
Figure 1 shows two of the most common variations of PWM switching topology—the buck and the boost converter—boiled down to their basics. In a synchronous configuration, a second transistor would replace the diode. In a sense, the use of pulse-width modulation makes these converters quasi-digital, at least compared to 723-style linear regulators based on a series-pass element. In fact, PWM makes it possible to use digital control loops. However, the converters in Figure 1 lack the circuitry that controls the duty cycle of the switch or switches, which can be implemented in either the analog or digital domain.
VOLTAGE-AND CURRENT-MODE CONTROL
Whether analog or digital, there are two ways to implement the feedback loop: voltage mode and current mode. For simplicity, first consider how they're implemented in the analog domain. A thorough discussion is available in Maxim's Application Note AN2031 (http://pdfserv.maxim-ic.com/en/an/AN2031.pdf).
In a voltage-mode topology, a sample of the output voltage is subtracted from a reference voltage to establish a small error signal that's compared to an oscillator ramp signal (Fig. 2). When the circuit output voltage changes, the error voltage also changes, which in turn alters the comparator threshold. In turn, this will vary the output pulse width. These pulses control the on-time of the regulator switching transistor. Pulse width decreases as output voltage tries to increase.
One advantage of current-mode control is its ability to manage the inductor current. A regulator using current-mode control has a current loop nested within a slower voltage loop. That inner loop senses peak currents in the switching transistors and keeps those currents constant, pulse-by pulse, by controlling each transistor's on-time.
Meanwhile, the outer loop senses dc output voltage and supplies a control voltage to the inner loop. In the circuit, the slope of the inductor current generates a ramp that's compared with the error signal. When the output voltage sags, the controller supplies more current to the load (Fig. 3).
In these control topologies, the gain around the control loop must not exceed unity at any frequency where phase shift around the loop reaches 360°. Phase shift combines the intrinsic 180° that results from feeding the control signal into the inverting input of the feedback operational amplifier, the additional delays in the amplifiers and other active elements, and the delays introduced by capacitors or inductors ( especially the output filter's large capacitors).
Stabilizing the loop requires compensation for gain variation and phase shift over a range of frequencies. Historically, stabilizing a power supply with analog PWM generally required an empirical approach: Try out different combinations of passive components on an actual circuit board with the same layout as the production board, and observe the circuit's time-domain response to changes in supply voltage and load demand. Recently, this has become easier. Analog controller companies now implement their own versions of various "plug a value into a register" capabilities first introduced for digital controllers.
DIGITAL CONTROL LOOPS
One of the best explanations of switching-supply digital control is in the white paper "An Introduction to Digital Control of Switching Power Converters" by Artesyn's Geof Potter. It can be found at www.astecpower.com/whitepaper/dcdc/. (This URL reflects Artesyn's acquisition by Emerson Network Power in February. Astec is part of Emerson.)
The paper describes a voltage-mode control topology, but the discussion can be extended to current mode. Most digital implementations of voltage-mode control comprise an analog-to-digital converter (ADC), a microcontroller or DSP implementing some control law, and a digital pulse-width modulator (DPWM) that takes the controller's output and generates the signals necessary to drive the transistor or transistors that perform the switching (Fig. 4).
First, the ADC produces a succession of digital representations of the output voltage that are fed to the controller. The control law is either the familiar proportional-integrating (PI) or proportional integrating/differentiating (PID) algorithm.
In a PID controller (the more complex example), an algorithm that's based on a series of coefficients operates on each ADC input. The proportional coefficient is a gain factor that's related to sensitivity. The integral coefficient adjusts the PWM duty cycle according to how long an error is present. The derivative coefficient compensates for time (effectively phase) delays around the loop. Taken together, the coefficients in the PID algorithm determine the system frequency response.
Using its control law, the controller translates the ADC's representation of output voltage into the pulse-duration (duty-cycle) information necessary to maintain the desired output voltage. This is then sent to a DPWM that performs the same drive-signal generation function as its analog counterpart.
Note the difference in how the switching transistors are managed in analog and digital schemes. The analog controller triggers the switching transistor ON at a clock transition and triggers it OFF when a voltage ramp reaches a preset trip voltage, while the PID controller calculates the desired duration of the switching transistors' ON and OFF periods.
In theory, analog control offers continuous resolution of the output voltage. But the interaction of the ADC resolution and sampling rate, plus the DPWM switching rate, make things a little tricky.
For instance, the DPWM must have finer resolution than the ADC. Otherwise, a 1-LSB change in the ADC output could cause the DPWM to shift the output voltage to a level greater than what the ADC sees as 1 LSB. As a result, the output voltage would toggle between two values in the steady state, a situation called "limit cycling."
Avoiding that cycling isn't necessarily easy, though. That's because giving the DPWM finer resolution means stepping up its pulse rate. (Pulse rate determines how many bits can be generated in any given time period.) However, the DPWM pulse rate limits the time it has in which to compress all those bits from the controller. The example that's in the Artesyn white paper addresses a hypothetical DPWM with a 1-MHz switching rate and a 10-bit ADC. Calculations show that the modulator would require a pulse rate greater than 1 GHz.
Such a high rate is impractical, of course, so digital controller designers must come up with an alternative solution. One is to introduce some DPWM clock dither. The regulator output filter averages any pulse train that's fed into it. That makes it possible to adjust the width of every mth output pulse by the equivalent of 1 LSB.
This increases or decreases the average value of the resulting pulse train by (1/m) times the resolution of 1 LSB. If 1 LSB at the controller input moves the output pulse train average by 10 mV, which shortens every fourth pulse by an amount of time corresponding to 10 mV, the average output voltage through the filter then will reduce by 10 mV/4 or 2.5 mV.
While almost all digital controllers use ADCs and stored-program controllers, this isn't the only possible approach. Last year, Zilker Labs noted that achieving the kind of step responses (hundreds of amperes per nanosecond) imposed by the latest Pentium-class processors required a pretty fast and, therefore, power-hungry DSP or micro in the controller.
As a lower-power alternative, the company introduced a controller based on comparators (rather than an ADC) and a state machine (rather than a stored-program approach). (See "PMBus Controller Takes A State Machine Approach" at www. electronicdesign.com, ED Online 11614.)
Furthermore, the simple buck and boost topologies described earlier aren't the only ways to accomplish digital regulation. Vicor presents a vastly different approach based on a much more sophisticated regulator topology than the simple buck or boost described above and a repartitioning of the elements in the power-distribution paradigm. (See ED Online 3185, 5948, 9092, and 11119 at www.electronicdesign.com.)
In the long run, digital control was a breakthrough technology. But many of digital control's benefits have now migrated back into analog-control regulators.
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