==================================Electronic Design UPDATE e-Newsletter Electronic Design Magazine - http://www.planetee.com February 26, 2003
=============================You've received this e-newsletter for one of two reasons: 1) you subscribe to Electronic Design magazine 2) you've signed up for it at http://www.planetee.com Please see below for unsubscribe and address-change instructions. Today's Table of Contents: 1. Editor's View -- Commentary 2. News -- From The Editors 3. Upcoming Industry Events 4. Magazine Highlights ********************** 1. Editor's View -- Exclusive to Electronic Design UPDATE ********************** The Ties That Bind: EDA And Test Are Now Inseparable By David Maliniak, Electronic Design Automation Editor A concept that came into vogue some years ago was that of design for testability (DFT). In the realm of ASIC/system-on-a-chip (SoC) design, DFT has been part and parcel of efforts to ensure manufacturing yield. Economics being what they are, it's incumbent upon design houses and foundries to reach for the best possible compromise between performance and yield. Today's mainstream methodology for manufacturing test is automatic test-pattern generation (ATPG). For 10 years or more, designers have used ATPG tools to insert scan cells after synthesis to the gate level. The resulting scan chains can then be accessed through a few external ports, and all of the registers in the design are exercised to ascertain that they are basically functional. Given its longevity and success, ATPG is not going away. But ATPG has its limits, and those limits are now being realized as process geometries have hit the 130-nm node with 90 nm on the horizon. ASICs and SoCs are pushing gate counts of 5 million to 10 million at these nodes, and here's where the traditional usage of ATPG and scan begins to run out of steam in terms of effectiveness. ATPG is great for stuck-at tests, creating static vectors to comb the design for hard failures in which nodes are literally stuck at one or zero. Unfortunately, the stuck-at fault model isn't going to cut it for nanometer-era design. EDA vendors are seeing increased demand from customers for tools supporting an at-speed test methodology to uncover the roots of failure mechanisms that are not static, but rather dynamic in nature. Such speed-related failures are generally the result of resistive nodes or bridges that cause transitions to slow down. Static vectors alone won't catch these. So what's now in vogue is a complementary mix of ATPG/scan and at-speed methodologies with an eye toward much more complete fault coverage. The latter is supported largely by what used to be known as built-in self-test (BIST) structures but is now called embedded test. There are some issues related to the volume of test-vector data that embedded-test methodologies generate, but these are ably handled by compression techniques native to the tools. Yet the combination is proving effective in nailing down a much higher percentage of faults than the previous methodologies were capable of. For the design engineer and EDA tool user, what the new test methodologies do mean is that DFT, which was once more or less a back-end issue, now has propagated both forward and backward throughout the design process. Embedded test structures are instantiated as intellectual property at the register-transfer (RT) level, making test a concern at various levels of abstraction. EDA tool flows are more mindful of test than they ever have been, looking at how to incorporate testability not only in flattened design views but in hierarchical views. Embedded test is highly compatible with hierarchy, making it an advantageous methodology. Look for EDA vendors to continue to make test a priority going forward. Partnerships with foundries and ATE manufacturers have sprung up to cement the relationships between the tools, the test hardware, and the design process. The end result can only be good news for everyone. Bringing up yields, after all, is in everyone's best interest. Contact Dave Maliniak at: mailto:[email protected] ********************** 2. News -- From The Editors ********************** ***Optimization Tools Boost Analog/Mixed-Signal Designs The release of Analog Design Automation's Creative Genius v2 and IP Explorer v2 tools answers the need for high-quality optimization tools for chip designers. Creative Genius v2 can optimize up to 200 devices across 60 environmental and manufacturing variations, with more than 30 performance goals. IP Explorer v2 is a tradeoff-analysis tool that allows multidimensional visualization of multiple circuit variations. http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07EJ0AF ***Simplify Peripheral Interfaces By Adding LVDS Serial Ports Expanding the flexibility and performance of low-voltage differential signaling (LVDS) into the peripheral world, designers at National Semiconductor have created several prototype circuits, including a high-speed interface (a dual physical layer, or PHY), a system test access device, and an analog-to-digital converter (ADC). All the chips include a serial LVDS interface that reduces the pin count, minimizes signal noise, and allows the chips to be located farther away from the host without reducing performance. The DS90LV049 interface circuit is a dual LVDS PHY transceiver that the company expects can be used in applications such as next-generation ink-jet and laser printers. The chip can handle data at up to 400 Mbits/s. Also released were details of the SCANSTA112, a chip that enables extended JTAG test and programming throughput an entire backplane. The chip is also an addressable JTAG multiplexer with seven local scan ports, so the circuit can be used from design debug and manufacturing test all the way through field repair and upgrades. The LVDS-enabled 10-bit, 40-Msample/s ADC, although not a final product, demonstrates how LVDS can be leveraged to drastically reduce the number of pins connecting the ADC to the host system. Samples of the LVDS PHY and test interface circuit are available immediately for $1.99 and $9.50 apiece in lots of 1000. Prototype samples of the ADC are also available. Its price has not yet been established. For more information, call (800) 272-9959 or go to http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07xo0Ah ***Power-Amplifier Software Optimizes Output Linearity The 89604A distortion-test suite speeds up the process of generating accurate, predistortion curves for linearizing the output of multichannel power amplifiers. The suite, developed by Agilent Technologies, can be used with the company’s ESA-E or PSA series spectrum analyzers or 89600-series vector signal analyzers. When used with a spectrum analyzer, the ESG or PSG series digital signal generator, and a PC running any current Windows operating system, the 89604A delivers the processed (delay-corrected and amplitude-normalized) signal files designers need to program advanced curve fitters that control the linearity of amplifier outputs. The test suite also graphically shows the incremental signal degradation contributed by the amplifier, as well as many other characteristics useful for optimizing amplifier performance. In addition, the software provides complete, time-aligned stimulus/response data, resampled to match user needs, for input to the predistortion curve fitter, which the designer would otherwise need to compile manually. The distortion test suite is available now for approximately $2000. For more information, contact Agilent Technologies at (800) 452-4844 or check out http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ0IjM0AD ***DiskOnChip Density Hits 64 Mbytes By leveraging an internally developed double-density technology (X2) and Toshiba's 130-nm NAND-based multilevel storage cell (MLC) technology, designers at M-Systems have boosted the storage capacity for its novel disk-on-chip flash-disk product to 64 Mbytes/chip. The resulting Mobile DiskOnChip G3 can replace rotating media in many code and data-storage applications. The 64-Mbyte chip operates from either a 1.8- or 3.3-V supply and provides hardware protection for code and data storage. Cascade options permit up to four devices to be connected to form a storage array of up to 256 Mbytes. The chips include a robust error-detection and error-correction code specifically optimized for the MLC technology to provide high data integrity. Additionally, flash endurance is maximized through the use of the true flash file system. The memory has a multiburst read speed of 80 Mbytes/s and an erase speed of 30 Mbytes/s. Access time is 45 ns. For data protection, the chip incorporates a 16-byte unique identifier number and has a 6-kbyte user-controlled one-time programmable storage area. There are two configurable write and read-protected partitions for data and boot operations. Housed in a 7- by 10-mm BGA package with 85 contacts (or a 48-lead TSOP-I), the DiskOnChip's small size suits it well for many portable and handheld applications. On standby, the chip draws just 10 microA. When active, the chip draws about 25 mA. Samples of the 512-Mbit DiskOnChip G3 are immediately available. Contact M-Systems at (510) 494-2090 or http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07xp0Ai Contact Toshiba Corp. at (800) 879-4963 or http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07xq0Aj ***Linux Phones Home Motorola recently announced that its new A760 cell phone will be running Monta Vista Linux. The color-screen phone incorporates a digital camera, MP3 audio player, and video player. It will also run Java applications. For more information, go to http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ0HtD0AD or http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07xr0Ak ********************** 3. Upcoming Industry Events ********************** March 3-7, DATE 03, Munich, Germany. Europe's pre-eminent conference on EDA and test will feature a total of 237 technical presentations that will span a wide range of topics. For more information, go to http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07ci0AG March 3-7, SAE 2003 World Congress, Detroit. This show covers a range of automotive technologies in its more than 1000-paper technical program, including extensive coverage of electronics topics. See http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07w60Aj or call (877) SAECONG. March 3-5, Flexible Displays and Electronics 2003, San Francisco, http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07w70Ak or call (207) 781-9800. March 10-14, HDI Expo 2003, San Jose. This conference and exposition for the design and manufacture of advanced circuits, high-density interconnect, semiconductor packaging, and related substrate technologies is co-located with PCB West. See http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07w40Ah April 22-26, Embedded Systems Conference, San Francisco. This show will present more than 140 conference sessions, including tracks concentrating on system-on-a-chip designs and consumer electronics. Topics will include security, WiFi, audio and video, Linux, and real-time design. For more information, go to http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07w80Al April 23-24, The Military and Aerospace Electronics East Show with COTScon, Baltimore, Md. See http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07xA0Av or call (603) 891-9267. June 2-6, Design Automation Conference, Anaheim, Calif. DAC has long been the EDA industry's premier venue for product announcements, technical presentations, and networking. For more information, go to http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07w50Ai June 10-13, JavaOne, San Francisco. Go to http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07xM0A8 ********************** 4. Magazine Highlights ********************** In case you missed them, here are some of the high points of our most recent issue, February 17, 2003. * Editorial -- We Need Safe End-Of-Life Disposal Programs To Save Our Environment * Point Of View -- Taking Chip-Scale Packaging To New Heights * Cover Story -- Battery Management Chips Empower Portable Designs Improved charging ICs and fuel gauges maximize Li-ion runtimes. * Leapfrog: First Look -- Fast-Turnaround ASIC Platforms Speed Complex Chips To Market By using preselected market-segment-specific blocks of IP, a new class of ASICs helps accelerate product development and trim costs. * Design View -- Boost Internet-Based Applications With Embedded Device Gateways The chaos of diverse physical systems can be transformed into an orderly and uniform set of software interfaces that bridge to high-speed networks. For the complete Table of Contents, go to http://lists.planetee.com/cgi-bin3/flo/y/ePk30DJhUf0EmQ07xN0AA
==================================CONTACTS: Electronic Design UPDATE e-NEWSLETTER
==================================Editorial: Lucinda Mattera, Associate Chief Editor: mailto:[email protected] Advertising/Sponsorship Opportunities: Bill Baumann, Associate Publisher: mailto:[email protected]
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