Electronic Design

Fast-Turnaround ASIC Platforms Speed Complex Chips To Market

By using preselected market-segment-specific blocks of IP, a new class of ASICs helps accelerate product development and trim development costs. One of the biggest challenges in ASIC design is reducing the design time from concept to final, functional silicon. To accomplish that, several companies have devised ASIC platforms with pre-integrated and qualified functions and interfaces to cut design time and verification. These include LSI Logic Corp., NEC Electronics America Inc., PalmChip Inc., and Toshiba America Electronic Components Inc.

The idea of a fast-turnaround design platform for ASICs isn't new. In the early days of gate arrays, several companies pre-integrated various functional blocks, such as multipliers and bit-slice processors, to reduce design time and achieve higher performance than if the same function were implemented using the gates of the gate array.

Blocks like the multiplier and bit slice are minuscule next to complex blocks such as MPEG decoders, DMA controllers, and RISC CPU cores. Though design libraries let designers use predesigned blocks, many of the blocks may not have been co-integrated. That means there are few guarantees they'll all work together. Thus, providing pre-integrated resources or prequalified sets of functional blocks still rings true.

Toward that end, LSI Logic just unveiled phase two of its RapidChip fast prototyping concept. The RapidChip's basic concept was unveiled in 2002. It combines the advantages of ASICs and FPGAs in a scheme that also minimizes or eliminates their disadvantages. This is accomplished by leveraging the company's CoreWare library of system building blocks, a customizable high-performance logic technology, and a new methodology and tool set optimized to reduce design cost and cycle time. The outcome is a solution that delivers twice the performance and 15 times the density of leading FPGA solutions, but at just 10% of the cost. This approach can considerably reduce system design time and nonrecurring engineering costs.

The LSI Logic StreamSlice series, the first system-on-a-chip (SoC) platform to emerge from the RapidChip program, is optimized to handle high-speed data-communications applications (Fig. 1). LSI isn't alone in the effort to shorten design and manufacturing times, however. Just last month, PalmChip released its AcurX SoC platform. Late last year, Toshiba exposed its SoCMosaic platform-based design approach. NEC Electronics America is finalizing its SoC design platform, which was unveiled earlier. These quick-turnaround silicon platforms will reduce NRE charges and keep mask costs under control. This becomes more critical than ever, as the cost for a set of masks for a multimegagate design in 0.13-µm technology can approach $1 million. These new platform approaches can slash close to 50% of the mask costs months from the design cycle.

But just offering a generic solution isn't enough. That's why LSI Logic released the partially configured "slices," which will target specific market segments. The first, the StreamSlice (the L79301), is optimized for communication-system designs. Its starting platform delivers 20 Gbits/s of full-duplex throughput for high-end switches, routers, and other communication applications.

To determine what functions system designers would most likely need, LSI Logic examined many communication systems and spoke to a number of system architects. From those discussions, it found a common set of functions—Ethernet ports, memory controllers, SPI 4.2 interfaces, and high-speed serial interfaces, among others—that all applications would typically need. Based on the research, the company "collected" these blocks into a predesigned chip (the StreamSlice) and ensured that the blocks all play together.

That takes a considerable burden off chip designers, because now they only have to focus on crafting the unique part of the design that adds their company's unique intellectual property to the mix. That value would be added by using LSI's customizable logic technology, which offers 3 million usable ASIC gates and five levels of metal interconnections. As part of the additional logic that may be included, off-the-shelf functions could be configured in the gate region by using soft cores from LSIs CoreWare library, further speeding the design.

So exactly what did LSI pull together on the StreamSlice silicon? Three million user-configurable ASIC gates exist supported by 40 HyperPHY interfaces that can each deliver data at 622 to 832 Mbits/s (that translates into two SPI 4.2 interfaces if the serial peripheral interfaces are needed). A dozen GigaBlaze serial interfaces can operate at data rates from 1.0625 to 3.25 Gbits/s. These interfaces can be grouped to form either two XAUI ports, up to eight Gbit Ethernet ports, eight Fibre Channel ports, or eight InfiniBand ports.

Pre-integrated on-chip are 2.6 Mbits of single-port SRAM (16 blocks of 2048 words by 80 bits) and another 640 kbits of dual-port SRAM (32 blocks of 256 words by 80 bits). The StreamSlice also packs a double-data-rate (DDR) memory controller with dedicated delay-locked loops (DLLs) (80-bit wide memory bus) for off-chip DDR DRAM, seven phase-locked loops (PLLs) for clock distribution and timing control, and 427 user-configurable I/O cells.

By doing much of the "hard" work, pre-integrating the high-speed IP and ensuring it works, LSI considerably reduces the designer's burden. In turn, that shortens design-cycle time from typically more than a year to perhaps under six months. This first StreamSlice version is just the beginning. LSI plans additional versions that pack more pre-integrated memory, gates, and high-speed I/O ports. Other options would let LSI add embedded processors, such as MIPS or ARM engines, or even DSP engines like the ZSP cores it acquired over a year ago.

In its new AcurX platform, Palmchip incorporated several new technologies. A novel on-chip networking scheme reduces routing congestion problems. A timing tap technology lets designers retime signal paths to achieve timing closure more quickly. And, a matrix interconnect approach significantly improves throughput and memory flexibility. Toshiba's SocMosaic option rapidly customizes complex SoC designs by using commodity IP blocks, standardized bus interfaces, a scalable bus system, an RTL testbench, and high-level cycle-accurate C simulation. In NEC's Instant Silicon Standard Platform, designers embedded blocks of SRAM, DLLs, and PLLs for timing; complex multigate programmable logic blocks; and test circuitry (Fig. 2). Just two metal layers are implemented to customize the logic.

For more details, go to:
• www.rapidchip.lsilogic.com • www.necel.com
• www.palmchip.com • www.chips.toshiba.com.

TAGS: Toshiba
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