Authors of bestselling literature don't just tap out their latest novel on a laptop while sipping a martini. They research the subject matter to give the narrative a voice of authority. Next they carefully outline the plot, then fill in the story. It's a wonder that chip design isn't always approached as judiciously as writing a bestseller, with each project started after looking at the big picture.
Striving for a practical and effective solution to enable system-on-a-chip (SoC) design is an electronics company's strategic weapon. An optimized system-level design flow can cut chip development time in half. Such a flow offers a practical solution and a way to transition from inefficient design methods to new approaches that handle tightly integrated SoCs.
A system-level design approach can help organize the design project and keep it on track. System-level design aids engineers in determining which architecture is best, along with how to partition a chip's functionality between software and hardware. A system-level design strategy gives an engineering team a means to work in parallel.
The flow covers design, which captures and animates the system specification. It also spans co-design for hardware/software partitioning, interface design and co-simulation, co-implementation that includes design refinement in parallel and co-verification, and intellectual-property (IP) reuse.
A TRANSCENDING LANGUAGETo accurately capture the overall specification, use a system-level design language—one that transcends hardware or software implementation. SystemC, for example, augments C/C++ with easy definition of blocks, support for concurrent execution, and ways to separate behavior and communication. The specification includes both the design and the testbench. So even at this early stage, the overall system functionality can be validated and fully debugged. This creates an executable, implementable specification that's reusable during co-design and co-implementation.The system-level design flow lets designers try different architectures with various hardware and software partitioning schemes and automates the synthesis of software device drivers and interface glue logic. This enables the design team to explore multiple "what-if" tradeoffs early in the cycle.
Gradually refining hardware partitions and optimizing software partitions by different teams in parallel gives the team the capacity for consistency with the original overall system specification—accomplishing covalidation through continuous coverification of the system. Less time is lost in the inherent back-and-forth process of traditional design methods.
IP reuse plays a growing role in hastening products to market. As more IP becomes available, or as organizations build their own, it'll need to be integrated into the system-level design flow for reuse in new systems. It's best that IP models be available at all levels of abstraction.
IC design teams should take a page from a bestselling author's playbook. Carefully plotting a chip's design from concept through tapeout may not result in a bestselling novel, but it will help speed up progress while cutting design costs.