Two-way debug feedback between chips and boards helps eliminate doubt when it comes to whether faulty behavior is in the chip or on the board. To enable this two-way validation, interoperability between ASSET InterTech and Mentor Graphics Tessent products for the IEEE P1687 Internal Joint Test Action Group (IJTAG) embedded instrument standard will allow engineers to debug and isolate issues in complex system-on-chips (SoCs) or on the circuit board where the chip has been deployed.
IJTAG resources—including embedded instruments and the network connecting the devices—are inserted into a chip with Mentor’s Tessent solution. Subsequently, engineers can verify and characterize the SoC’s functionality and performance at the chip level. When used on a circuit board, ASSET’s ScanWorksTool provides a debug loop by accessing IJTAG resources to isolate problems in both the SoC and the circuit board. Issues found at the chip level can then be corrected before fabricating additional devices.
In light of ever-more-complex SoCs and increasing numbers of integrated IP blocks, IJTAG helps maintain the rapid pace of new product introductions. IEEE’s statement of scope for the standard says,
This standard will develop a methodology for access to embedded test and debug features, (but not the features themselves) via the IEEE 1149.1 Test Access Port (TAP) and additional signals that may be required. The elements of the methodology include a description language for the characteristics of the features and for communication with the features, and requirements for interfacing to the features.
The two companies will also collaborate on several educational programs and workshops to jump-start the adoption of IJTAG.