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Libero SoC v11.4 Software Improves FPGA Runtime Up To 35%

Libero SoC v11.4 Software Improves FPGA Runtime Up To 35%

According to Microsemi, its updated Libero System-On-Chip (SoC) version 11.4 software reduces design flow runtime by up to 35% and timing analysis runtime by 20% for the company’s SmartFusion and IGLOO FPGAs. For greater efficiency, Microsemi enhanced the SmartDesign graphical design canvas as well as text-editor, design-reporting, and constraints-editor capabilities. In addition, SmartDesign Generation and System Builder run two times faster. File import also runs two times faster. Upgraded SERDES wizards feature new clocking options to increase flexibility when mixing serial data rates. A key addition is full design flow suppot for the Linux open-source operating system. A FlashPro Express tool comes bundled with the software to enable device programming and debugging capabilities for the Linux operating system. Support is included for the test bench at any level.


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