A high-performance, low-cost transistor technology for microprocessor and system-on-chip (SoC) devices at the 45-nm node and beyond can be implemented without making major changes to current fabrication processes. The process was developed by Renesas Technology, which has used the process to create complementary metal insulator semiconductor (CMIS) transistors with a hybrid structure employing metal gates for p-type transistors and conventional polysilicon gates for n-type transistors. Prototype devices with a gate length of 40 nm exhibit excellent performance. Their drive capacity is 620 µA/µm for n-type transistors and 360 µA/µm for p-type devices. In addition, there were no problems with reliability, in terms of factors such as gate dielectrics.
The trend toward very small semiconductor processes has resulted in thinner gate dielectrics. This has created problems such as increased leakage current due to the tunneling phenomenon. One effective solution is to use high-permitivity (high k) dielectrics on top of an oxide silicon film. But this causes what's called "Fermi-level pinning," which creates a high transistor threshold voltage. The use of metal gates can suppress this phenomenon and is though to be essential at the 45-nm mode and beyond.
This led Renesas to develop the hybrid CMIS transistor. The high-k dielectric is made of hafnium silicon oxynitride. It can formed simply by adding fluorine ion implantation and minimal processing of a titanium nitride layer to the earlier fabrication process. The transistor's performance meets or exceeds that of conventional dual-metal-gate devices. For more information, visit www.renesas.com.