Electronic Design

Programmable Framer Chip Improves OC-48 Efficiency

Using virtual concatenation, a next-generation Sonet chip allocates bandwidth dynamically, facilitates provisioning, and preclassifies and tags packets to free up network processors.

Synchronous optical networks (Sonets) are clearly the workhorse of the telecommunications industry. Sonet rings and point-to-point connections form wide-area networks (WANs) that carry most long-distance voice communications and form the backbone of the Internet. Now Sonet is being widely employed in metropolitan-area networks (MANs) to provide local access to WANs.

Although Sonet was invented as a way to carry large numbers of digitized phone calls in T1/T3 format, today it's routinely used to carry packet data as well. In fact, Sonet can be made to carry data in almost any format, although it doesn't always do so efficiently. The high-speed fiber-optic link in the network is typically underused, and those paying for it only receive a fraction of its capability. But Cypress Semiconductor's new POSIC chip promises to change all of that.

The CY7C9536V Packet Over Sonet/SDH with Integrated Concatenation (POSIC) chip is a multiservice platform that allows designers of next-generation network equipment to take advantage of the wide bandwidth available in an OC-48 (2.488-Gbit/s) channel. At the same time, voice and a variety of data formats can be transmitted on the same channel. This chip allocates bandwidth by implementing the new ANSI virtual concatenation standard. It permits virtual linking of multiple low-order Sonet/SDH streams inside of a higher-order link to provide a right-sized bandwidth pipe for high-speed LAN traffic. The POSIC chip is the first chip to support this key standard.

The basic function of a framer chip such as POSIC is to assemble and disassemble Sonet frames. Each frame, called a synchronous payload envelope (SPE), is a standard 810-byte block consisting of 27 bytes of overhead and 783 bytes of data. The base data rate is 125 µs per SPE, or 51.84 Mbits/s. For transmit operations, the framer builds the SPE from the input data to be transmitted, adding all necessary overhead. Multiple SPEs can be sent within 125 µs to form an OC-48 stream.

In the receive mode, the framer recovers the data from the SPE and sends it to the processing equipment. The POSIC chip then communicates the data over a Universal Test and Operations Interface for ATM (UTOPIA) bus to ATM equipment. There, ATM packets are segmented, reassembled, and then sent to a LAN or some constant-bit-rate (CBR) ATM service. Alternatively, the chip may communicate with a WAN data-link layer device or network processor through a POS-PHY bus. The received data is deployed by the host processor for possible transmission to other LAN/WAN ports or a backplane switch fabric.

POSIC is designed to be built into routers, switches, add/drop multiplexers, and other equipment, such as edge concentrators or broadband aggregators (Fig. 1). It connects to an OC-48 line via optical interface components and a transceiver IC, such as the CY7B9532V from Cypress that performs clock recovery and generation, as well as serial-to-parallel and parallel-to-serial conversion.

POSIC isn't just a hot new chip looking for a killer application. Instead, it provides solutions to a number of problems associated with high-speed networking. It's a packet-over-Sonet/SDH (POS) framer designed to transmit ATM and other packet data over Sonet links. POSIC operates at OC-48, OC-12 (622-Mbit/s), and OC-3 (155-Mbit/s) rates. It solves the data-transmission inefficiency problem of POS by using the new ANSI virtual concatenation standard to allocate bandwidth dynamically.

POSIC provides secure and optimally sized bandwidth provisioning for transporting higher-speed data traffic, such as IP and ATM, using virtual concatenation (see "What Is Virtual Concatenation?" below). This method lets bandwidth be allocated in increments of STS-1 (51.84-Mbit/s) or STS-3 (155.52-Mbit/s) portions with up to 16 channels.

The chip also allows the transport of packets that are larger than standard SPE size, transparently, through the network. Without virtual concatenation, sending a 10-Mbit/s Ethernet signal over Sonet/SDH would require provisioning of an entire STS-1 channel but waste over 40 Mbits/s of the bandwidth. Similarly, transporting 100-Mbit/s Ethernet would require the provision of an STS-3 channel, with about 55 Mbits/s going unused on a network. Plus, there wouldn't be a way to send Gigabit Ethernet over an OC-48 pipe without using up all available bandwidth.

With virtual concatenation, POSIC can send, among other combinations, two different Gigabit Ethernet channels and still leave some bandwidth for other applications. This is extremely useful for emerging LAN transport applications in MANs.

POSIC can establish these connections within milliseconds. This means that carriers using equipment made with the POSIC chip can perform provisioning in minutes or hours, rather than the days, weeks, or even months common today.

A second major POSIC benefit is that it performs on-chip packet preclassification and tagging. This relieves external processors from having to analyze every packet in the system and making link-layer and buffer-management functions more efficient, freeing them for higher-priority processing. This feature increases the bandwidth for packet processing and queue management, guaranteeing the quality of service (QoS) so essential in today's systems.

POSIC's programmable frame-tagging engine allows networking system software to specify particular patterns in an incoming packet and direct POSIC to preclassify packets based on different bit fields inside of the packets. Preclassification eliminates the need for the host CPU to process every packet on every line card and helps to streamline switch-fabric operations to improve processing and system capacity.

Frame-tagging applications include PPP parsing, data/control packet separation, placing data/control packets in different buffers, looking up MAC addresses to determine if a packet belongs to the node, prioritizing packets in different priority queues, and identifying incoming MPLS labels. Frame tagging works over both packets and ATM cells.

In addition, POSIC further ensures efficient traffic engineering in systems using multiprotocol level switching (MPLS). It handles all parsing and label lookup for MPLS packets on-chip.

Finally, POSIC supports a wide range of new and proposed packet-framing protocols, including Lucent's Simple Data Link (SDL or ITEF rfc 2823), Nortel's Data Over Sonet (DOS or ANSI T1X1.5), and Cypress' own Hybrid Data Transport (HDT) protocol. The POSIC chip's generic optical network protocol framer delineates all of these types of packets with packet length and CRC information. This positions POSIC for use in virtually all next-generation networks.

POSIC contains over 3 million 0.18-µm CMOS transistors housed in a 504-pin BGA package. It does a lot more than simply perform the usual Sonet housekeeping chores (Fig. 2).

POSIC talks to the CY7B9532V transceiver over two 16-bit data buses using HSTL signaling. Transceiver-side processing includes Sonet framing and de-framing, as well as section, line, and path overhead (SOH, LOH, POH) processing. Sonet framing can be bypassed in applications where data is transmitted directly over fiber in a non-Sonet form.

Next, virtual-concatenation logic allows the data to be transmitted and placed into multiple Sonet SPEs, or removed from SPEs in its original protocol format. This sophisticated logic manipulates the Sonet/SDH overhead bytes so that different packet sizes and types can be mixed as necessary. In addition to standard Sonet formatted data, POSIC can handle ATM, Ethernet, and other types of packets. It permits the transmission and recovery of packets that are larger than the standard SPE too.

Inside the POSIC chip are three transmit and receive processors called engines—an ATM engine, an HDLC engine, and a generic protocol engine. These processors handle all packet assembly and disassembly, formatting, and the related chores.

In the receive path, a programmable frame-tagger engine identifies and tags packets. The engine parses and sorts the packets, appends a tag, and stores the tag in a buffer for use by the external processor as desired.

The protocol determines the interface to the LAN/MAN/WAN side of the chip. In ATM systems, a 32-bit UTOPIA bus is employed, as defined in the ATM standards. For other packet protocols, such as Ethernet and HDLC-like formats, a 32-bit POS-PHY bus is used. A separate 32-bit bidirectional bus is provided for the external processor.

Price & Availability
The CY7C9536V POSIC chip will be available in sample quantities in June. Full production is expected during the third quarter. It's priced at approximately $335 each in quantities of 1000.

Cypress Semiconductor Corp., 3901 N. First St., San Jose, CA 95134; (408) 943-2600; www.cypress.com.

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