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RTL Design Verification Tool Eliminates Learning Curve

Designed to be easy to use by eliminating the learning curve normally associated with formal register transfer level (RTL) design verification technology, BlackTie is offered as a functional checker and full-chip, multi-million gate capacity tool that accelerates the verification of system-on-a-chip (SoC) designs. The application verifies monitors and includes an open source assertion monitor library written in the Verilog hardware description language (HDL).
By providing verification early in the design cycle to find as many RTL problems as possible, users of the verification tool can formally check assertion monitors to find deeply embedded bugs. Among other things, it can also automatically check for global errors, asynchronous clock domain crossings and dead-end states. BlackTie supports Hewlett-Packard, Sun Microsystems, and Linux operating systems and costs $75,000.


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