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As the semiconductor industry shifts to 0.13-µm and smaller devices, IC designers must strongly consider materials issues.
The substrate material upon which chips are built can profoundly affect design structures, interconnects, and other critical design considerations, particularly when advanced circuit materials, such as copper and low-k, are used in device manufacturing.
Innovative enhancements supporting silicon-on-insulator (SOI) have made SOI attractive for next-generation systems-on-a-chip (SoCs). But to get the full benefits from SOI, the industry must optimize SOI design processes and methodologies.
SOI improves device speed by 15% to 35% over that exhibited by bulk CMOS technology. This speed upgrade represents two years of bulk CMOS advances. A lower threshold, reduced junction leakage (when compared with bulk CMOS), and low junction capacitance give chip makers the tools to master standby current and reduce device power consumption by more than half.
Getting the most out of SOI's benefits, whether fully or partially depleted, requires knowledge of the how the SOI material behaves. At this point, the article goes into depth on Spice modeling of SOI circuits. In particular, the contrast between using fully and partially depleted devices in Spice simulation is highlighted. The article states that standard bulk models can be used if key parameters are modified, but ultimately an accurate circuit simulation can't be achieved. On the other hand, the electrical behavior of partially depleted devices is similar to bulk devices, therefore they can be modeled identically.
Developing a library for an SOI design kit is another key point addressed. SOI design kits aren't currently available, so library requirements are provided here.
|SOI Simulation Challenges||To get an optimized SOI circuit design, an SOI model is needed to help the designer understand the SOI transistor's behavior. Such models must be implemented in a Spice circuit. Several SOI models currently reside in commercial Spice simulators.|
|Fully Depleted SOI Simulation||Though not completely accurate, a Spice simulation of SOI circuits using fully depleted devices can be performed using a standard bulk model if key parameters like junction capacitance and current, as well as threshold voltage are modified.|
|SOI Design Kit Requirements||Unlike bulk CMOS, design kits for SOI aren't currently available. ASIC design requires a design kit composed of a library of standard cells, I/Os, and RAM and ROM compilers. Developing a library requires an established characterization methodology.|
|Sidebar: Smart-Cut Process||SmartCut technology uses ion implantation and wafer bonding to make the UNIBOND SOI wafers. Hydrogen ion implementation acts as an atomic scalpel, enabling thin slices of monocrystalline film to be cut from a donor wafer.|
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By employing the proper models, designers can fully understand SOI transistor behavior and come up with successful circuit designs. As the semiconductor industry shifts to 0.13-µm and smaller devices, IC designers must strongly consider materials issues. The substrate material upon which chips are built can profoundly affect design structures, interconnects, and other critical design considerations, particularly when advanced circuit materials such as copper and low-k are used in device manufacturing. Thanks to innovative process enhancements that support very thin films, silicon-on-insulator (SOI) is gaining ground in this area. In fact, major chip makers, including AMD and IBM, openly endorse its use for next-generation systems-on-a-chip (SoCs). Yet to fully exploit SOI's benefits and enable production of large volumes of SOI-based devices with deep-submicron features, the industry must turn its attention to optimizing SOI design processes and methodologies.
SOI technology improves device performance, or speed, by 15% to 35% over that exhibited by bulk CMOS technology. Needless to say, the industry is rapidly moving toward SOI as the most common substrate for building advanced CMOS-based (complementary metal-oxide semiconductor) SoCs. These devices are used in applications like mainstream microprocessors for handheld systems, and other emerging wireless electronic devices requiring low power consumption.
The immediate improvement offered by SOI is roughly equivalent to two years of bulk CMOS advances. SOI-based transistors provide a lower threshold voltage, which lets designers reduce power-supply voltage without sacrificing performance.
In addition, because silicon thickness is minimized, junction leakage on SOI is considerably reduced compared to bulk CMOS—both at room temperature and higher operating temperatures. Together with SOI's low junction capacitance, these advantages enable chip makers to master standby current and reduce device power consumption by more than half. Using a typical inverter as an example, Figure 1 depicts how much design space is saved using SOI compared to bulk CMOS.
SOI SIMULATION CHALLENGES
An SOI transistor differs from a bulk transistor in that its body (the internal substrate) isn't externally biased—unless a specific layout is used, such as in a body-contacted transistor. There are two types of SOI devices: fully depleted and partially depleted. The terms partially and fully depleted refer to the channel region of a transistor. In both methods, the source and drain regions are depleted down to the oxide. Channel depth is where the two approaches differ. Partially depleted SOI channels aren't depleted down to the oxide, yet they are in depleted chips.
For completed devices to take full advantage of SOI's benefits, whether fully or partially depleted, circuit designers need to use specific techniques to help them address various challenges. In particular, they must pay attention to the behavior of the SOI material, which differs significantly from that of bulk CMOS. Optimized SOI circuit design can only be achieved if an SOI model is employed to help the designer understand the SOI transistor's behavior.
To accurately describe the SOI device's electrical behavior, SOI models must be implemented in a Spice circuit simulator (Fig. 2). While some companies develop their own SOI models for internal development projects, several models currently reside in commercial Spice simulators. These include BSIMPD, derived from the popular BSIM3 bulk model, and BSIM3SOI at the University of California, Berkeley; SOISPICE at the University of Florida; and STAG at the University of Southampton (England).
SOI design company Soisic currently uses the LETISOI model developed by French research organization LETI (Laboratoire d'Electronique, de Technologie et d'Instrumentation), where both Soisic and SOITEC were incubated and eventually spun out as standalone companies. SOITEC's proprietary Smart Cut process for SOI wafer manufacture is described in the accompanying sidebar (see "Smart Cut Process Technique—An Overview"). Soisic will soon introduce its own model, derived from LETISOI, called PHYsical MOdel for SOI Simulation (PHYMOSS).
All of these models mainly address partially depleted SOI metal-oxide semiconductor field-effect transistors (MOSFETs); SOISPICE and BSIM3SOI can handle fully depleted SOI transistors as well. The PHYMOSS model will also address fully depleted devices in a future release.
Simulating with an SOI model requires more CPU time, as the body is an additional floating node whose self-bias is determined by the Spice simulator. Convergence of the Spice simulator is a critical point when using SOI, as the simulator has to solve Kirchhoff's Law, stating that the sum of all current components at one node must equal 0—sometimes, at very low current levels. For example, in the dc condition, the impact ionization current must equal the body-source junction current. The body potential results from this balance. Extra nodes are generally added to account for both self-heating (all types of devices) and body-resistance (only body-contacted devices) effects. Thus, the netlists used for SOI circuit simulation typically differ from those used for bulk CMOS.
FULLY DEPLETED SOI SIMULATION
A Spice simulation of SOI circuits using fully depleted devices can be performed using standard bulk models if some key parameters are modified, such as junction capacitance and current and threshold voltage. But an accurate circuit simulation can't be achieved. For instance, the threshold voltage expression of a fully depleted device depends on the silicon film thickness and doping level, the buried oxide thickness, and the back-gate bias (bias applied to the substrate below the buried oxide). This parameter isn't accounted for in a bulk model. Moreover, when the silicon film is fully depleted, the body can't be accessed. Body-source and body-drain capacitors no longer exist. Only the direct source-to-drain capacitor remains, and it has quite a low value if an ultra-thin silicon film is used.
Advanced (0.13-µm and below) fully depleted devices require an ultra-thin silicon film (less than 25 nm thick) to control two-dimensional effects known as short-channel effects. This is when the threshold voltage (VT) heavily depends on the gate length. It also is referred to as VT roll-off. Fully depleted devices generally only provide low-VT transistors. The need for high VT to reduce the off-current (current leakage that fixes the standby current) will require implementation of partially depleted transistors (thicker silicon film or higher doping level). Full depletion is imposed by the gate potential when the depletion depth extends across the whole silicon film.
However, in accumulation regime (negative gate-to-source voltage for NMOSFET), the transistor shifts from fully to partially depleted. In addition, taking the NMOSFET as an example, the impact ionization mechanism injects holes into the internal body. The corresponding charge may compensate the depletion charge and lead to the suppression of full depletion. In turn, the internal body potential may rise enough to trigger a parasitic bipolar transistor. This result should be avoided as much as possible, since electrically modeling these transistors requires using a complex model to perform the time-consuming process of predicting transitions between fully depleted and partially depleted operation.
The electrical behavior of partially depleted devices is similar to that of bulk devices, where the substrate or well node is left floating. Therefore, it can be modeled identically. But none of the parasitic components can be neglected due to the frequent self-biasing of the body by effects from the impact-ionization current (known as substrate current in bulk devices) and bipolar parasitics responsible for breakdown of bulk MOSFETs.
Also, lateral junction components—namely, current and capacitance—are modified in partially depleted devices due to the limited silicon thickness. Thus, a partially depleted SOI model, although similar to a bulk model, requires a highly accurate description of all current and charge components. In particular, the model must be able to tolerate a strong forward body bias, which is at the origin of threshold voltage lowering and parasitic bipolar conduction (also known as the kink effect).
The SOI transistor's internal body is influenced by any external variation. Impact ionization occurs when the drain voltage increases and the body is capacitively coupled to all other terminals. This means that the threshold voltage depends on each bias condition. But its value can be accurately predicted by a dedicated SOI model.
Many different transistor layouts can be implemented with partially depleted devices, permitting independent management of the body bias. The threshold voltage is then statically or dynamically modulated by applying different body voltages using body-contacted devices. Yet body-contacted transistors are useless with fully depleted devices because the silicon film is too thin, causing a corresponding body resistance that is too high. The thinner the silicon film, the higher the self-heating effect that must be considered for both fully and partially depleted devices—particularly at low-frequency operation (typically less than 100 MHz).
Finally, the most intrinsic and important feature of SOI technologies, isolation, brings major benefits. For one, there's no latch-up. Also, because SOI transistors use a small volume of silicon, they're intrinsically less sensitive to radiation. The latter is the historical reason for SOI's use in military and space applications, albeit with much thicker films than those needed for today's consumer, communications, and computing devices.
SOI DESIGN KIT REQUIREMENTS
Cell layout and sizing are very different when using SOI technologies instead of bulk CMOS. The transistors' unique electrical features, whether fully or partially depleted, require different sizing to attain optimal performance. This ultimately affects design rules. As a result, direct migration of existing bulk CMOS libraries to a CMOS/SOI process yields poor performance as neither density nor speed is improved.
Unlike bulk CMOS, design kits for SOI aren't currently available. ASIC design requires a design kit composed of a library of standard cells (or gates), input/output cells (I/Os), and RAM and ROM compilers. Developing a library requires an established characterization methodology whereby all cells are simulated to determine their speed and power performance, while accounting for different load configurations. The methodology must also account for possible variations in process technology, power-supply voltage (±10%), and operating temperature (usually 0°C to 100°C).
For partially depleted SOI technologies, the methodology should also include propagation-delay variations caused by floating-body effects. The threshold voltage of such devices is affected by any external variations that change with time. This "history effect," named because the speed of a gate at a given time depends on its previous states, must also be accounted for in the design methodology.
Using a predictive SOI model is the best way to minimize the history effect's impact on partially depleted devices. The magnitude of the history effect depends on the gate type (e.g., inverter, NAND, NOR, XNOR, latch), but it's relatively small compared to all other possible variations (process, supply voltage, temperature). Even with this effect, SOI gates perform better than their bulk counterparts. They benefit from lower junction capacitance, lower threshold voltage, and lack of substrate effect, enabling optimal stacking of transistors. When the simulation shows that floating-body effects may affect the behavior of a critical circuit path, advanced design techniques are required.
SoCs clearly represent the future of electronic products. But integrating more and more functions into one chip will only be possible if power consumption is minimized. This means using all applicable design options (power-supply and clock management, implementing in hardware versus software). It also means reducing the power-supply voltage and, in turn, lowering the threshold voltage to maintain performance and increase leakage current.
With its low-threshold-voltage capability, SOI offers a solution to this dilemma. Fully depleted devices provide low sub-threshold swing and intrinsic capacitance. Partially depleted devices deliver low off-current with a high static VT and low dynamic VT (VT is reduced when the gate switches).
Because SOI substrates provide the high degree of isolation between functions that SoCs require, single-chip SOIs for high-performance devices such as wireless products are expected to become popular. As designers employ creative thinking to explore new ways to use SOI transistors, novel concepts like one-transistor DRAMs are emerging. The need for these kinds of new ideas will only increase as bulk CMOS approaches the physical limitations of its usefulness. High-resistivity SOI substrates are a real plus, while high-quality passive components can be implemented on substrates that exhibit low high-frequency loss.
Designers must understand that SOI isn't revolutionary, but rather part of the natural evolution of substrate materials. As with all aspects of semiconductor development, this evolution is essential to the future of SoCs and other advanced devices.
Designing ICs on SOI is rapidly becoming a mainstream technique, although it does require a thorough understanding of the SOI material to develop a design approach that fully exploits SOI's benefits. Figure 3 depicts a design flow optimized for SOI features. This is easiest to accomplish when designers work closely with SOI process and material providers.