Electronic Design

Switches Aggregate 16 Ports Of Fast Ethernet And Add QoS

The ZL5041x Ethernet switches make it possible to cost-effectively aggregate 16 ports of 100-Mbit/s Ethernet and incorporate the quality-of-service (QoS) features that are becoming a necessity in many Ethernet systems. These chips are designed for metro access equipment, media gateways, edge routers, passive optical networks, very high-speed digital subscriber line access multiplexers (DSLAMs), and local-area network (LAN) workgroup switches.

The switches are well suited for handling time-sensitive voice and video traffic in convergent networks. Moreover, they permit profitable time-division multiplexing (TDM) access, such as T1/E1 leased lines, to be delivered with carrier-grade quality over Ethernet networks.

The ZL50417/418 chips integrate 16 Fast Ethernet ports with two Gigabit Ethernet ports to deliver nonblocking throughput at a rate up to 7.2 Gbits/s. These switches can forward up to 10.712 Mpps (millions of packets per second). The ZL50415/416 chips also have 16 Fast Ethernet ports and can achieve nonblocking throughput up to 3.2 Gbits/s and forward up to 4.7 Mpps. The Gigabit ports, which provide Layer 2 forwarding and Layer 3/4 classification, are fully programmable. Their data-rate control lets service providers tailor the bandwidth to individual customers.

The QoS features add further flexibility. Each port has up to eight output queues that can be programmed to differentiate traffic based on its priority level. The queues map to, and provide full support for, the eight traffic classes in the Internet Engineering Task Force (IETF) Differentiated Services Set. The set includes network management, expedited forwarding, assured forwarding, and best-effort classes.

The ZL50418 switches use scheduling algorithms to minimize the output delay of queued traffic. The algorithms manage a combination of prioritization schemes, such as delay bound scheduling, weighted fair queuing, and strict priority. Delay bound scheduling guarantees output delays of less than 160 ms in heavily congested conditions. Congestion management is provided using weighted random early detection.

These chips are in production now. Zarlink also has a comprehensive system reference design to speed time-to-market.

Zarlink Semiconductor

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