EE Product News

SystemC Capability Boosts EDA Application

The company has added SystemC capability to its A|RT Designer architectural synthesis EDA tool. Users can now start a system design at a high level in MATLAB, SPW or COSSAP and take it to a synthesizable Verilog or VHDL description using the SystemC language. Floating point ANSI C code can be refined to fixed-point SystemC code either manually or automatically using tools such as Synopsis' CoCentric fixed-point designer.
The fixed-point SystemC description is read directly by the designer application without any language penalty. The designer is then used to explore architectural alternatives and generates Verilog or HDL when the optimal architecture is found.
Prices for the A|RT Designer start at $65,000 per seat.


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