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Verilog Simulator Claims 6X Performance Gains Over Earlier Versions

In version 5.0 of the VCS Verilog simulator, dramatic performance gains are claimed through the integration of the previously acquired Radiant Design technology with the VCS RoadRunner cycle-based algorithms. Doubling of performance during the design debug and analysis process are said to be made possible thanks to an optimized IEEE standard programmable language interface (PLI) and a direct kernel integration with leading graphical analysis environments. In addition, VCS 5.0 now includes post-simulation graphical analysis capabilities.The Radiant Design technology optimizes Verilog designs, making them more compact and efficient for simulation. The result is significantly faster performance that requires no changes to the design methodology. It uses design analysis techniques that exploit the inherent redundancy and uniformity of the Verilog HDL at any level of abstraction.Also, significant enhancements for design debug and analysis have been incorporated in the form of optimized PLI and direct-kernel integration. The PLI is used as the primary interface to allow third-party tools to integrate with the simulator. It's been optimized to provide up to two times the simulation performance when integrating with third-party or custom-designed PLI routines. In addition, VCS 5.0 provides better debugging performance through the introduction of a direct-kernel integration between commercial GUIs and VCS. This interface is available with Summit Design's VirSim tool- the graphical analysis environment that now ships with VCS (see story below)- and Novas Software's Debussey product. Over 150 technology libraries from semiconductor vendors are available for use with VCS 5.0.VCS 5.0 is available immediately. It's available for most UNIX platforms including Solaris, SunOS, HP-UX, DEC Alpha, IBM RS6000 and SGI as well as for Windows 95/NT-based systems.


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