In certain situations, a 50% dutycycle signal can pass through a transformer
without problems, providing there's a negative half-cycle to completely demagnetize
the core. However, if the core isn't wholly demagnetized, a buildup of energy
can occur, and eventually the core saturates and the pulse no longer can pass
through the transformer. In general, low frequencies aren't a problem because
the core is only magnetized for a small part of the pulse period. But high frequencies,
typically those used in microprocessor-timing and logic circuits, can cause
saturation problems in the core due to magnetic energy build-up, particularly
when transitions are between zero and a positive voltage.
This setup (Fig. 1) overcomes the
problem of passing 50% duty-cycle signals through an isolating transformer.
It sends narrow edge-triggered pulses through the transformer and regenerates
the 50% signal on the other side of the isolation barrier. The circuit consists
of a positive-and negative-edge trigger, an OR-gate logic driver, and a D-type
flip-flop divider. The edge detectors produce narrow pulses. Their pulse width
can be determined by selecting the appropriate R and C values (tp
≈ 2ΠRC). The narrow pulses are combined
at the OR gate to yield a frequency-doubled signal with a narrow pulse width.
Pulse widths of less than 50% allow the core to easily desaturate during the
"off" cycle. The 50% duty cycle is regenerated using a D-type flip-flop
frequency divider connected on the other side of the isolation barrier.
Using a 500-kHz signal and standard 74LS logic, timing results (Fig.
2) were produced for the resistance and capacitance values shown in
the circuit of Figure 1. Higher frequencies
are accommodated by reducing the capacitor's value and, if necessary, using
faster logic gates. This circuit's most likely applications would be in data
bus isolators where data exchange is at high frequency, and when passing a clock
signal through an isolator.
