Electronic Design

Double Maximum Load Current With Two Parallel Converters

Automotive, industrial, and FireWire peripherals all call for high-efficiency, space-saving power supplies with high current capabilities at very high voltages. The problem is that high-voltage, monolithic (where the power switch is included) high-current buck converters aren't always beefy enough to handle the required load currents.

One solution is to parallel two converters and double the maximum load current. However, a few modifications to the standard buck-converter configuration are required to maintain load sharing and stability between the two converters and reduce input and output ripple.

Figure 1 shows an 8- to 40-V input, 5-V output at 4-A maximum load current, dc-dc converter. It uses two LT3430 60-V monolithic, 3-A (peak switch current) buck regulators in parallel. The ICs are synchronized at up to 250 kHz with a 180° phase shift between the two using the LTC6902 multiphase oscillator with spread-spectrum frequency modulation (SSFM). Figure 2 shows the efficiency of the circuit in Figure 1.

Synchronization is important because the fixed 200-kHz switching frequency varies slightly from part to part. If the two parallel converters are allowed to run at different frequencies, the output ripple may, over time, carry some undesirable low-frequency ripple components that equal the difference in frequency between the two ICs.

Running the two ICs 180° out of phase reduces input and output ripple. Usually, one IC is increasing current while the other IC is decreasing current, allowing the ripple current of one to counteract the ripple of the other. This minimizes stress on the input and output capacitor energy banks. On the other hand, if the two ICs are operated in phase, both ICs would demand current out of the capacitors and would send current into the capacitors at the same time on each cycle. This effectively doubles the ripple of the circuit over that of a single IC.

The SSFM mode of the synchronization signal from the LTC6902 is set between 235 and 250 kHz. This reduces the peak EMI that would be observed had the switching frequency been fixed at 250 kHz. Changing the jumper position (grounding the modulation pin of the LTC6902) defeats SSFM mode and sets the frequency to 250 kHz.

Given the proper layout, at around 40% to 60% duty cycle, the two-converter circuit requires half of the capacitance that's needed for a single high-current IC circuit with a 4-A load current. In applications that demand a wide range of duty cycles, the two-IC ripple is a little more than half of the single-IC ripple.

Over a wide range of loads, the optimal setup for thermal and efficiency considerations is when both ICs evenly share the load. This is achieved by tying the outputs of the error amplifiers (VC pins) together. The differences in the two error-amplifier and feedback-network gains are removed. Additionally, the parts can work together within the tolerances of the inductors and modulator gains. Current sharing is approximately even in this design over the entire load-current range.

Two separate 2.5-A, 22-µH power inductors are better than one much larger 5-A, 10-µH inductor because their collective volume is smaller than the volume of the single inductor by a factor of 2 . This minimizes overall component height.

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