Efficiency is a prime objective in solar energy systems. In conjunction with its Japanese partner, the Kaneka Corporation of Osaka, Imec has demonstrated a 6-in. semi-square heterojunction silicon solar cell that achieves a conversion efficiency of nearly 23% via an electroplated copper contact grid positioned on top of a transparent conductive oxide layer.
Created at the Kaneka Osaka laboratory, this development uses the company’s copper electroplating technology. Silver-screen printing generally is preferred for creating the top grid electrode in heterojunction silicon solar cells. But it’s extremely difficult to keep resistance low while thinning the metal line in silver-screen printed contacts.
Failure to keep resistance low means efficiencies will be less than optimal. Costs stay high as well. So, Imec and Kaneka are replacing the screen-printed silver with electroplated copper, which meets the resistance objectives.
Stack Engineering—A New Approach
Imec also is boosting the performance of resistive RAM (RRAM) cells with new approaches to stack engineering. These approaches, Imec claims, will improve the general understanding of RRAM process technology and facilitate scalability and improved manufacturability of RRAM technology.
RRAM technology is very fast and economical in terms of power. It also has good scalability and is compatible with CMOS processes. Its operation relies on the voltage-controlled resistance change of a conductive filament in the dielectric of a metal/insulator/metal (MIM) stack.
RRAM systems based on hafnium oxide (HfO2) offer excellent scaling capabilities and high reliability. These advantages are attributed to efficient voltage-controlled management of oxygen motion in the stack during switching.
Imec has already demonstrated asymmetric bipolar RRAM cells with high performance and very low operation current (<500 nA). This technology was created by employing a hafnium scavenging layer, which is the key element in the stack asymmetry of defect distribution and in the forming process.
Also, Imec has made progress in the performance and reliability of RRAM cells by process optimisations that are paving the way for RRAM scaling down to the single-digit nanometer scale. A newly developed patterning of the resistive element (RE), using an optimised house-developed etch chemistry, significantly reduces the oxidation at the RE sidewall and increases the cell’s performance, says Imec. The SiN-last (silicon nitride) RE encapsulation improves the cell’s reliability (107 cycles of endurance even after 60 hours of bake test at 250°C).
Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu, Toshiba/Sandisk, and Sony are key partners in Imec’s CMOS programs. During its work with those organizations, Imec has advanced the testing and evaluation of options for further transistor scaling using high-k dielectrics and metal gates in a replacement metal gate (RMG) integration schema.
Although RMG technology is far more complex than gate-first integration, its advantages include increased device performance and the provision of greater choice of high-k and metal gate materials. One of the current challenges to enable further device scaling is the choice of gate dielectric and gate electrode.
For the selection of the gate electrode, the key considerations are the work function, resistivity, and CMOS compatibility. Further scaling also requires continued improvement of the channel mobility, adding the options for improved stress management and reliability control as a first-order consideration in the choice of materials and processes.