Electronic Design

Enhanced Logic, Clock Management Give FPGAs 500-MHz Internal Speed

Designing high-speed digital systems on FPGA platforms has always been challenging. The large amounts of routing required by SRAM-based FPGAs often limits system performance to well below that possible with ASICs.

But thanks to a novel Supercluster logic module, an efficient routing scheme combined with antifuse configuration elements, and a high-speed clock-distribution network, Actel Corp. of Sunnyvale, Calif., has crafted a family of antifuse-based FPGAs that can hit internal speeds of over 500 MHz. Such high clock rates will let systems implemented in the FPGAs operate at over 350 MHz and handle more complex functions than ever before.

The Supercluster architecture the AX family uses was derived from the company's sea-of-modules approach used in the SX family. The Supercluster modules cover almost the entire surface of the AX-series FPGA chips, with virtually no area lost to interconnect elements or routing channels.

Each Supercluster contains combinatorial and register-based cells as well as transmit and receive routing buffers (see a drawing of the architecture at www.elecdesign.com under Forefront). The combinatorial cells can implement more than 4000 combinatorial functions of up to five inputs, while the register cells pack a flip-flop with asynchronous clear and preset inputs and programmable clock polarity.

On the larger family members, 336 Superclusters are grouped with a quartet of 4-kbit blocks of SRAM to form a core tile. The SRAM blocks are grouped in a vertical line on the west side of the core tile. The first chips in the family, the AX1000 and AX2000, will pack 3-by-3 and 4-by-4 arrays of core tiles, respectively. This yields an equivalent system-gate complexity of 1 million and 2 million gates, respectively.

The Supercluster architecture is fully fracturable as well. If a particular signal path uses one or more logic modules in the Supercluster, the other logic modules are still available for use by other paths. Clusters of I/O blocks and an I/O bank ring surround the array of core tiles. Each block in the I/O cluster contains two I/O modules, four receive modules, two transmit modules, and a routing buffer module (again, see the details in the figure posted on our Web site).

The 64-bit FIFO buffer (bypassable if not needed) in each I/O module is unique to the AX architecture. The per-pin FIFOs can be organized into blocks of up to 26 pins. An embedded, dedicated FIFO controller can be used to control the I/O FIFOs. Or, the I/O FIFOs can be disassociated from the controller and individually controlled by logic formed in the Superclusters.

Samples of the AX1000 and AX2000 will be available in the fourth quarter of this year for $255 and $628, respectively, in volume. For more information, check out www.actel.com, or call (888) 992-2835.

TAGS: Digital ICs
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