Synthesis flows
As designers well know, today’s FPGAs are large enough to swallow a lot of functionality, which is a good thing. The bad news is that going from RTL to a bit file for these big chips is starting to take a lot longer than it used to, which begins to defeat the purpose of an FPGA. Yet as the cost of ASIC/system-on-a-chip (SoC) design pushes the $150 million range at 22 nm, FPGAs remain an extremely popular alternative to full-custom design.
In its latest release of the Synplify Pro and Synplify Premier FPGA synthesis tools, Synopsys has sought to improve runtimes with a fast synthesis mode. This mode is aimed squarely at designers who are prototyping ASICs on FPGAs. These users are interested in fast synthesis runs and don’t necessarily care about squeaking out the last iota of timing performance. It’s also useful to designers seeking a quick idea of the performance of their RTL and constraints. The fast logic synthesis mode offers up to a 4X speed improvement over traditional logic synthesis when using a single processor.
Runtime improvements come largely from the implementation of what Synopsys terms “automatic compile points,” a technology that intelligently breaks the design up into sections and locks down those that are not affected in a given synthesis run. This can result in runtime speedups of up to 30% over and above the fast synthesis mode speedup, the company claims. It also permits blocks to be processed in parallel, which lends itself to use with multicore CPUs.
Also new is a global placement technology. Users have the option of using either the Synplify global placer or the ISE global placer tool from Xilinx in physical synthesis flows (see the figure). Overall quality of results with the Synplify placer is comparable to that achieved with the Xilinx tool, but somewhat faster, Synopsys says.
Physical synthesis flows can suffer from long iteration times through logic synthesis and placement. To aid this situation, Synplify Pro and Synplify Premier now offer a physical accelerator flow for use after the initial synthesis run. This flow runs all the way through to a final netlist that’s ready for loading onto the FPGA. But if this version doesn’t meet performance requirements, the tool can start over from that netlist and revise some of the place-and-route data from the initial run to improve timing.
Lastly, with FPGA design becoming a task for larger teams that are often geographically dispersed, the tools must adapt for such scenarios. In this release of Synplify, the tools support a concurrent development environment that encompasses top-down, bottom-up, or hybrid flows. The overall idea is to make it easier for dispersed teams to collaborate in scenarios where one team might have a full block done while others may still be in a black-box stage.
This first phase of a team-design implementation automates what many design teams may be doing today using scripting in a painful, manual process. Synplify now makes it easier to engage in concurrent development and to synchronize and integrate changes made in dispersed locations. It also makes it easier to reuse design modules and to deliver status reports to team leaders. The reports come by virtue of a new hierarchical project manager, a GUI that facilitates project tracking and reporting as well as top-level integration.
Finally, the new Synplify versions add support for the SiliconBlue iCE65 mobile FPGA family as well as the Altera Stratix-V device family. The tools support all Synopsys DesignWare building-block digital components for instantiation, except for macrocells (such as an 8051 controller).
The 2010.09 release of the Synplify Pro and Synplify Premier products is available now and can be obtained directly from Synopsys through SolvNet by existing customers under maintenance. The Synplify FPGA synthesis products are supported on Windows and Linux (32- and 64-bit platforms).