Electronic Design

Read white paper: An FPGA Design Security Solution Using a Secure Memory Device

This white paper provides a solution to help protect FPGA designs from being cloned. Using the “identification, friend or foe” (IFF) design security approach, this solution disables the design within the FPGA until the hash algorithm computation matches in both the FPGA and a secure memory device, so the design remains secure even if the configuration data bitstream is captured. In this solution, the secure memory device is use as a security companion chip for the FPGA. Download this brief form to access this important paper.

TAGS: Digital ICs
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