With increased usage of embedded memories in today’s deep submicron ICs, access to their inputs/outputs is a major concern. If this access is impaired, it limits the capability to apply standard tests, leading to different testing schemes that tend to be very intensive. As a result, more test-development and test-application time is needed.
Limited access to the inputs/outputs can hamper our ability to test for certain types of faults. Also, the inability to do an in-system, at-speed test can allow some critical performance-related faults to go undetected, seriously compromising the quality of the product. A viable solution to test embedded memories is built-in self-test (BIST).
BIST is a design-for-testability technique in which testing (test generation, test application and output data evaluation) is accomplished through built-in hardware. Incorporating BIST hardware in each embedded memory alleviates the accessibility problem and creates self-contained and autonomously testable memories (Figure 1).
BIST results in a uniform testing methodology that fosters standardization and test reuse. It also allows a simple and uniform interface protocol to be used between the device-level BIST control and each embedded memory. A self-contained BIST approach for the whole device can be adopted to simplify the execution of BIST.
Consider an embedded memory in a chip in a board that is part of a system. A top-down hierarchy consists of the system, board, chip and embedded memory. If all levels use BIST, the system can test an embedded memory by sending a control signal to the board which, in turn, activates self-test on the chip and returns the results to the system. Consequently, BIST allows for an efficient hierarchical test strategy to overcome the difficulty of testing embedded memories on ICs.
This hierarchical test strategy helps reduce the development effort and cost of testing circuitries at the chip, multichip module (MCM), board and system levels. Because tests are generated internally as they are being applied, rather than being pregenerated, stored and applied externally, BIST offers a superior solution in which the test equipment and the test program become much simpler. The same BIST hardware is reused for testing chips, MCMs, boards and the entire system during manufacture and in the field.
As the complexity of ICs increases, there is no simple way to design BIST for every embedded memory. A designer needs automated synthesis tools to incorporate BIST in embedded memories. Such automation reduces the test development effort not only at the IC level, but also at the board and system levels because BIST is a hierarchical test and can be reused at different levels of integration.
Even though the introduction of memory BIST increases the device hardware, it minimizes the cost of production test and more than pays for itself over the life of the product. At the board and system levels, BIST improves troubleshooting and diagnostic efforts, and reduces the manufacturing interval and the costs of maintenance and repair.
The quality of a product greatly depends on its test to identify a faulty product. Tests for different types of embedded memories, such as RAMs, ROMs or FIFOs, must be calibrated according to their ability to detect physical defects.
Physical defects manifest in different ways depending on the type of memory they are in. Specific fault models are derived for each type of embedded memory corresponding to the manifestation of physical defects. The test quality depends on how realistic the derived fault models are.
Embedded memories, such as RAMs, FIFOs and ROMs, offer unique testing challenges in each case. The regularity of their designs allows a denser packing of logic and interconnections. As a result, such structures are susceptible to a wide set of faults which continue to grow with the increase in miniaturization to deep submicron technologies.
In read/write-type memories, such as RAM or FIFO, stuck-at, transition, retention, stuck-open, coupling and multi-access faults must be detected. Deterministic algorithms (as opposed to pseudorandom) are generally adopted for read/write memories. The algorithms typically provide high fault coverages, more than 99% specific to the structure’s fault types and function.
Deterministic test algorithms are structure-specific. That is, without fault simulation, they exploit the functional and structural characteristics of the regular structure in question and yield a guaranteed fault coverage.
These algorithms can either be specific to give regular structure design, in which case the physical layout information and the design of the surrounding blocks are taken into consideration; or generic, where no access to the design specifics is assumed. The first often results in shorter and more customized test algorithms, which sometimes require certain design-for-testability features in the memory design. Generic algorithms often require longer test length with multiple sets of background data and do not use any design-for-testability.
The effectiveness of BIST depends on the adopted fault models and test algorithms. Not all BIST algorithms yield the same level of defect coverage.
Since the number of embedded memories per device is in continuous growth, and since the BIST algorithms of each type of embedded memory are often different, then individual BIST controllers must be allocated to each embedded memory. Generally, the BIST controllers are customized finite state machines for a given test pattern generator (TPG) or output data evaluator (ODE). The complexity of the state machine is a function of the BIST algorithm used for a given embedded memory.
Sharing the BIST hardware for identical embedded memories is very cost-effective. The potential savings increases as the number of blocks sharing the same BIST hardware increases.
For example, if two RAMs share the same BIST hardware, the area required per RAM to implement BIST is reduced by nearly 40%. An example is shown in Figure 2, where the three RAMs share the BIST controller, the TPG and the test address generator. The ODEs for each RAM are separate; consequently, separate BIST flags are held for each RAM.
The test time becomes an issue when a device goes into manufacturing. The cost of testing goes up as the test time increases. Sharing BIST hardware also executes BIST simultaneously for all three RAMs, which reduces the test time.
BIST on embedded memories is often invoked through the boundary scan (IEEE 1149.1) port by executing the standard RUNBIST instruction. This sets the boundary scan cells to the mode in which the chip logic is isolated from its board environment, enabling the device to perform a totally autonomous self-test. When BIST is complete, the compacted signature is scanned out through the boundary-scan port and compared to its expected value.
BIST is one of the most promising test solutions. With the increasing quality requirements, complexity and operating frequencies of electronic products, BIST can provide a comprehensive solution for device, board, system and field test.
About the Author
Yervant Zorian joined AT&T in 1987 and is a member of the Technical Staff in the Test and Reliability Center at AT&T Bell Laboratories. He received an Ms.C. degree from the University of Southern California and a Ph.D. in electrical engineering from McGill University. AT&T Bell Laboratories, P.O. Box 900, Princeton, NJ 08542-0900, (609) 639-3176.
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Copyright 1995 Nelson Publishing Inc.
September 1995
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