In preparation for the 1995 International Test Conference (ITC), the Quality Test Action Group (QTAG) is working to adopt a standard monitor for quiescent current (IDDQ) testing. This article provides background on QTAG, describes the challenges that face QTAG as the group develops and evaluates a new monitor circuit, and offers several potential solutions.
As a method of device testing, IDDQ has long been both important and problematic to the semiconductor industry. IDDQ testing can detect faults not detected with traditional functional (voltage) testing, by measuring current flowing through the VDD pin of a device while the device is in a quiescent state–thus the term IDDQ).
Several studies have shown that traditional voltage testing does not find the most difficult faults. 1,2 For example, a gate-oxide short in a simple CMOS inverter can cause significant leakage in IDDQ, but will not cause the device to fail a functional test.
Figure 1
illustrates how IDDQ testing can identify a significant percentage of bad parts.1 This test case requires scan and functional test as well as IDDQ test to achieve 100% fault identification.
A good CMOS part draws current only when switching. The presence of higher-than-normal IDDQ can indicate gate-oxide shorts, bridging defects, open transistors and other leakage-related defects.
Throughout the 1970s, IC manufacturers used IDDQ to measure leakage in SSI and MSI CMOS parts. As devices have become increasingly complex, measuring IDDQ has become more difficult.
Larger scale integration, however, also means there is more need for IDDQ testing. As competition between IC manufacturers increases, so does the importance of overall product quality. Finding faults early becomes both more difficult and more important.
QTAG
QTAG, which grew out of the semiconductor test industry’s renewed interest in IDDQ, came into being at ITC ’93. The group consists of members from the IC industry and the academic community, all of whom have a stake in developing a standard method of IDDQ testing.
To meet throughput requirements and accurately identify failing devices, members of QTAG agree that the future of IDDQ testing depends on the development of a standard monitor device attached to a test fixture. Such a monitor, driven from a digital tester and returning a pass/fail value, must have sufficient dynamic current capability, and yet measure very small IDDQ.
Traditional IDDQ solutions have utilized a variety of techniques, most of which involve a parametric measurement unit which has limitations in the area of measurement and throughput. A fixture-based monitor would eliminate most of these problems by providing faster throughput.
Ideally, IDDQ monitors will be tester-independent; that is, they will be usable in a variety of test fixtures and driven by any digital tester. ATE end users stand to benefit significantly from a standard IDDQ monitor: A plug-and-play solution with a generic interface and standard circuit across all test systems would lower setup and test time while increasing fault coverage.
One of QTAG’s goals is to develop the standard for an IDDQ monitor. Early on, QTAG agreed that collaboration among IC manufacturers, ATE vendors, fixture vendors and the academic community was critical to QTAG’s success.
IC designers and manufacturers are the most active in QTAG because they have the most to gain. ATE vendors must develop the software interface between the monitor device and the tester. Their role in the development of an IDDQ monitor is to communicate requirements and participate in evaluation.
Fixture vendors must provide the location on fixture boards to meet the requirements for monitor setup. The academic community’s role so far has been to research and design monitor prototypes.
Shortly after ITC ’93, representatives from QTAG outlined a four-phase process to achieve the mission:
Define a monitor standard.
Design and build a prototype monitor.
Evaluate the standard monitor prototype.
Formulate an IEEE standard for the monitor.
QTAG first defined three classes of monitors according to size and functionality; for example, whether they perform pass/fail or analog measurements:
Class 1 Monitor–oriented for production test and chosen as the initial prototype, with a view toward expanding development to include other classes of monitor devices in the future.
Class 2 Monitor–oriented toward either production test or engineering characterization, with a medium footprint of approximately 2 cm x 2 cm to provide enough additional area for more complex monitor functionality.
Class 3 Monitor–with a footprint of 4 cm x 4 cm, to be used primarily in engineering characterization.
Class 1 represents a little-foot monitor, which would occupy a very small surface on the test fixture (approximately 1 cm x 0.8 cm) to facilitate mounting close to the DUT. Locating the monitor device within a few millimeters of the DUT minimizes the effect of parasitic inductance and still allows adequate decoupling of the device. To achieve maximum throughput, the device would return a pass/fail value.
QTAG Survey
During ITC ’94, the QTAG chair conducted a written survey of members, covering the projected applications and requirements for a QTAG monitor. The survey showed that most QTAG members are interested in IDDQ testing for consumer, telecommunications and data-processing applications. This focus may surprise ATE vendors, whose experience with the aerospace, military and automotive markets might lead them to expect those applications to demand the higher reliability associated with IDDQ testing.
IDDQ testing techniques enable you to view a large number of faults, offering a high fault coverage with relatively few measurement points. At the same time, IDDQ testing remains complementary to traditional functional and scan testing, and it is doubtful whether IDDQ testing will become the only test technique in low-cost applications.
Most survey participants wanted a monitor with a capability of at least 20,000 samples per second (S/s). For most respondents, the minimum acceptable rate was 10,000 S/s.
The vector sampling rate, driven by the number of vectors that must be measured, is an economic issue. In an environment where milliseconds can be translated into lost revenue, the relatively long test times involved in making current measurements can be very undesirable.
Given a choice of fixture locations for the monitor, the DUT board was the favorite for most respondents. However, they expressed concern about locating monitors on test fixtures, given potential problems with electrostatic discharge (ESD) and robustness.
While some of these problems are common to all IC development, the continuous contact that a measure pin has with devices, test after test, combined with the negative impact that protection against ESD can have on the monitor’s performance, creates more potential hazard to a fixture-based monitor than to devices being tested. In the larger scheme, however, QTAG members agree that the fixture is the best place for an IDDQ monitor.
The QTAG survey results have several implications for ATE vendors. First, the focus on IDDQ testing in consumer, telecommunications and data-processing applications suggests that test time is a significant issue for ATE IDDQ test capability.
Second, the market needs a solution beyond what is technically possible with traditional measurement methods using parametric or power supply measurement units. These have proved to be less than ideal vehicles for IDDQ testing because of relatively slow measurement time and, in the case of power supplies, low resolution of current measurement. The proposed QTAG monitors should be able to meet both of these requirements.
The QTAG Monitor
QTAG has formulated these technical objectives for developing the standard monitor:
Define a minimal-pin configuration package for a monitor, whose specific design may vary among manufacturers. Any digital test system must drive and receive information appropriate for IDDQ testing using such a monitor.
Create a pin configuration that demands packaging in a minimal number of package types to cover most applications needs.
Define a standard ATE interface and physical size that allows all common test fixtures, DUT boards, probe cards and contactors to be used.
Define VDD and VSS line-monitor configurations. VDD line monitors measure IDDQ, while quiescent ground wire currents (ISSQ) are measured by VSS line monitors.
Recommend or define multiple monitors and multiple power pin configurations.
Create a monitor description format that allows different monitor implementations to be easily driven by ATE hardware and software.
Allow tester selection of a variable IDDQ/ISSQ threshold.
Allow robust physical construction and reliable operation in a stressful ESD environment.
QTAG looked at a variety of proposals for Class 1 monitors, with the initial device, code-named IDUNA-2, developed by Philips Research and Lancaster University. Currently, the device is being evaluated by ATE manufacturers and end users. Key aspects of the objectives are being considered, including integration and ease of use.
Open Issues
Several issues require QTAG’s attention at ITC ’95 and beyond.
First, so far it has been a challenge to identify an obvious manufacturer for the monitor devices once a standard is adopted. Such manufacturing represents a new subset of the IC industry, and the market share is difficult to gauge. The relatively small number of monitor devices likely to be sold worldwide represents some risk from the standpoint of return-on-investment.
Second, the presence of active circuitry on the fixture board presents the risk that good devices will fail if the monitor circuitry ever malfunctions. Additionally, the presence of the monitor on the fixture makes it difficult to perform temperature testing.
Third, the extent to which the prototype IDDQ monitor under consideration actually meets the technical objectives established by QTAG is not clear. To date, the evaluation results have been mixed: Several users have had success with the monitors and others have had problems related to layout stability and high resistance in the monitor’s bypass transistor.
A Complete Solution
When performing IDDQ measurements in a production environment, you face two challenges. First, you must decide where in the vector set to make measurements. Second, you must identify a pass/fail threshold for IDDQ.
For most production applications, it is not always desirable to measure IDDQ for every vector. Such exhaustive measurements usually result in unacceptably long total test time. The ability to fault grade the vectors could help you select a minimum set of vectors to achieve a high fault coverage.
Test automation tools can select quiet vectors and fault grade these vectors by analyzing a circuit’s netlist and choosing the most appropriate vectors for IDDQ testing; that is, the least number of vectors that exercise the whole circuit. Such tools (for example, Cadence Design Systems’ VeriCurrent, CrossCheck Technology’s CurrenTest, or Sunrise Test Systems’ TestGen) usually achieve 100% fault coverage with a given set of vectors, due to the massively parallel nature of the IDDQ testing technique.
Statistical analysis of the IDDQ current drawn by known-good parts is currently the best technique for setting the current threshold for pass/fail testing. One possible solution is a source measurement unit (SMU) combined with a QTAG monitor and commercial software packages to identify IDDQ vectors for testing.
By using test automation tools and the Integrated Measurement System’s (IMS) SMU, quiescent vectors can be identified. This figure illustrates that not every vector is suitable for making quiescent measurements.
Data from the SMU can be input to a program to determine pass/fail limits which can, in turn, be used to program the monitor device. The monitor driver software sets the pass/fail threshold based on SMU characterization.
In our experience at IMS, the combination of the IDDQ monitor and the SMU is the most effective way to do IDDQ testing. This total solution allows a better standardization of the monitor to provide a more global solution on any ATE system.
Conclusion
IDDQ is now becoming accepted as a viable technique for improving the detection of faults which may not be detected using traditional test techniques.
In certain production environments, relatively slow IDDQ measurement times could affect throughput. As a result, engineers have investigated the use of monitor circuitry on the DUT fixture board that can achieve an acceptable measurement rate. QTAG offers a compact monitor solution with sufficient dynamic current capability and fast IDDQ measurement time to provide a good general solution.
As part of this solution, commercially available test automation tools can assist with quiet vector selection and fault grading to ensure that all parts of the circuit are covered by the selected vectors. Using an SMU to acquire IDDQ values for a sample of parts and statistically analyzing the measurements help in selecting a suitable IDDQ threshold for each device type.
The QTAG proposal could lead to commercially available monitors that would allow semiconductor manufacturers to standardize across their installed ATE systems. By using a standard solution, such companies would benefit significantly from not having to support their own monitor designs. Although the proposed QTAG solution may not meet the needs of all users, hopefully QTAG monitor devices will address the requirements of the majority.
References
1. Maxwell, P., Aitken, R., Johansen, V., and Chiang, I., “The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?,” Proceedings of the International Test Conference, 1992, pp. 168-177.
2. Baker, K., and Verhelst, B., ” IDDQ Testing Because ‘Zero Defects Isn’t Enough:’ A Philips Perspective,” Proceedings of the International Test Conference, 1990, pp. 253-254.
About the Author
David Leslie is a Senior Applications Engineer at Integrated Measurement Systems. Mr. Leslie received his B.Sc. in electrical and electronic engineering from Newcastel-upon-Tyne Polytechnic (Northumbria University) in the United Kingdom. His experience in field applications and support with IMS, Summit Design (formerly TSSI) and IKOS Systems has included assignments in Europe and the United States. Integrated Measurement Systems, Inc., 9525 S.W. Gemini Dr., Beaverton, OR 97005, (503) 626-7117.
Copyright 1995 Nelson Publishing Inc.
October 1995
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