Do you really need an extensive software suite to generate efficient high-quality test programs for mixed-signal devices? The answer depends on three factors: device characteristics, ATE architecture and product status.
Low pin-out devices require fewer ATE hardware resources, and therefore programming facilities, than high pin-out devices. Similarly, program generation for simple ICs is naturally less problematic than for complex ones.
The ATE architecture may be optimized to test a particular class of components or expandable to cater to a variety of mixed-signal devices. Software prompting for fill-in menu selections may be all that is needed for the former, while extensive sets of software tools could be required for the latter.
Product status–new design vs mature device–is the other major factor impacting software requirements. To shorten time to market for new ICs, a recent trend not only includes ATE instrumentation parameters during design simulation, but also develops DUT programs before the device physically exists. This is done via ATE emulation and DUT simulation, requiring modeling, data transfer and associated program manipulation tools.
Purchasing more software tools than you require is just as unacceptable as not having the program generation capability you need. Obviously, everyone needs the software that commands the test-station’s basic functions. But for most devices, DUT stimuli-generating software must also be available. And for some applications, simulation and emulation capabilities are essential, too.
All mixed-signal ATE is provided with the necessary software to help interconnect the appropriate resources with DUT pins. In some systems, the resources are shared and connected through switching matrices; in others, dedicated per-pin resources are provided. The software usually includes rule checkers to assure that no cross-connection conflicts occur and warn if programmed commands invoke unreasonable resource allocations or instrumentation settings.
Parameters for individual tests are entered via a graphical user interface (GUI) and menu entries. The resulting commands invoke digital or analog source outputs and DUT response evaluations. Test-management software is provided to assemble individual tests into test sequences and to inject programmed quantitative or pass-fail decision points.
When synchronization between digital and analog events is required, analog signals are transliterated into a digital format and generated by arbitrary waveform generators (AWGs). Similarly, analog responses are quantified by waveform digitizers to enable time-synchronized evaluations. Associated conversions or analytical computations are usually performed by digital signal processors (DSPs).
Writing DSP software is not an easy task, so preprogrammed algorithms for common functions (Fourier transforms, vector/scalar arithmetic or filtering) are usually provided. The test programmer may call these up individually or combine them to generate DUT-specific signals or results analysis.
“Comprehensive DSP libraries allow full characterization of data with high-level function calls,” said Paul Botsford, Principal Applications Engineer at Credence Systems. “An example is a call that operates on captured analog data that may return quantified SNR, THD, rms noise, fundamental magnitude and DC offset. Other high-level functions may return parameters such as frequency response or group delay.”
Function calls may be invoked by programs written in C or other convenient languages, but they are now more commonly called up through GUIs and icons. To provide still greater ease and versatility for generating composite DSP algorithms and result displays, object-oriented environments are also provided.1
Since all test-station programming commands are most readily entered via graphics and menus, many test-station control systems are now MS Windows-based. Some suppliers have chosen National Instruments’ LabVIEW, running on MS Windows or on workstation operating systems, as the foundation for their mixed-signal test station software.
For instance, the software for the Eagle ETS-500/D test system, which uses LabVIEW as a foundation, includes the ETS Shell management system, the TestBench resource and virtual instrument control system, and graphical program development facilities. Similarly, IMS provides the TestVIEW graphical program environment based on LabVIEW.
“The TestVIEW environment supplies graphical sequential test programming with transparent interfacing to instruments,” said Jim Graydon, Business Unit Manager, Mixed-Signal, at Integrated Measurement Systems (IMS). “More than 200 analog instruments are supported in addition to the complete functionality of the IMS Test Station. Interactions between the digital subsystem and the analog instrumentation are easily programmed and assessed. Extensive data manipulation, DSP functions, statistical analysis, graphing, plotting, file import/export capability and data logging are provided.”
Stimuli Generation and Response
Generating mixed-signal test stimuli involves obtaining a minimal, but sufficient, set of digital test vectors and generating analog or digitized-analog waveforms. Time coherence between analog and digital stimuli is usually mandatory.
DUT response evaluation examines the digital outputs, capturing and quantizing analog outputs and comparing these with expected results. Again, synchronization between digital or analog inputs or outputs may be critical.
Stimuli selection for simple devices sometimes may become obvious by mere examination of the DUT data sheet. For more complex devices, digital patterns may be obtained from automatic test program generation (ATPG) software packages, and analog stimuli from waveform generation software provided with AWGs.
When test programs must be generated for newly designed devices, it is always desirable to start by reusing test stimuli generated by the device designer. To facilitate this data transfer, most ATE includes import and translation software.
“For example, the HP 9490 system software has an ASCII Converter function,” said Jeff Hintzke, Product Line Manager, Mixed-Signal Test Systems at Hewlett-Packard. “You can easily transfer information from the design environment into a simple ASCII file which the HP 9490 software can read and translate into its required internal formats. This ASCII file is often generated automatically by a conversion routine written by HP, the customer or a third-party software tool provider like Simutest or Summit Design.
“Analog waveforms may be generated or modified with our graphical Waveform Editor tool,” Mr. Hintzke continued. “And digital vector generation and editing, as well as synchronization of analog sources and digitizers, are handled with our Vector Editor.”
Most mixed-signal ATE software enables you to develop and debug portions of programs without tying up the ATE hardware resources. “Off-line program execution and verification can be set up on the HP 9490 by playing back results from a file, simulating real device test results and flow,” explained Mr. Hintzke. “These off-line execution and result playback capabilities can also be used with a mixed-signal device simulator, such as Design And Test Engineering System (DantesTM) software from IMS, to allow even more complete test program debug.”
ATE Models in Design Simulation
Structuring the model of a device, simulating its performance and using simulation results to predict whether it will perform its intended functions are essential parts of the design process today. But the performance of the actual device can be determined only after it is connected to external circuitry, which initially is a DUT load board and the ATE.
If the expected real-world interconnecting circuitry is not adequately considered during simulation, results may be misleading and several time-to-market lengthening turns–including logic redesign, mask modifications and new silicon–may be required. If device testability is inadequate, more device redesigns may be required. To save time and money, interconnection- and test-related aspects must be considered during design simulation.
Several CAE companies address this issue. Cadence, for instance, has developed Dantes, an integrated software environment that gives design access to the test requirements and vice versa. Dantes is now marketed by IMS, a subsidiary of Cadence.
Dantes is built on the Cadence Artist Mixed-Signal Design System and integrated with the Cadence Allegro Board Design Development Software. Its basic functions include test capture and documentation, simulation, rule checking, code generation, test-fixture design and test-environment emulation.
To provide easy access to instrumentation models, Dantes contains the Cadence Virtual Tester generic library. The contents of this library were initially determined by considering resources available within the Teradyne A500 family, LTX Synchromaster and HP 9480 testers.2
Several other mixed-signal test system suppliers have since provided modeling information for the library. According to Steve Morris, Marketing Manager of the IMS Test Software Division, Dantes now supports test development for mixed-signal ATE from Teradyne, LTX, Credence, Hewlett-Packard and Advantest.
Developing and debugging test programs for complex mixed-signal devices can be a time-consuming process, with most of the time spent after the first device prototype is received. To make matters worse, much program debugging is done on the mixed-signal tester, tying up an expensive resource that should be used for production testing.
An integrated design and test-simulation environment can do much to lessen the time-sequential dependency imposed by waiting for silicon and can minimize required debug time on the ATE. Consequently, the main aim of Dantes is more than providing test- related information to the designer. Dantes allows the test engineer to build a test data base directly on top of the design data base, according to Mr. Morris.
The test-program generation process captures test schematics for each individual test that show how ATE instruments are attached to the device. This schematic-based test capture can occur very early in the design process, usually as soon as a device specification is available.
Parameter templates are used to “program” each instrument with timing, voltage and other test parameters. Each test schematic is then simulated so the test engineer can see how the device will interact with the test instrumentation.
Since each test schematic includes the device model and the instrument models, the timing architecture and analog characteristics of each instrument and the device are part of the simulation. To provide optimum correlation of simulation results with on-the-tester results, Dantes provides a test emulation interface called the ATE Link.
“The ATE emulator runs the actual test program and converts test-program events into simulation events,” explained Mr. Morris. “These events are passed to Dantes, which funnels them through the instrument models and the fixture model to the device model. Device responses are then funneled back to the test program for processing. Test results are displayed in the ATE environment in exactly the same way they would be displayed when driving a real tester.”
Two-Way Data Exchange
Although the test engineer may reuse the designer’s analog and digital test stimuli, additional program generation facilities, usually provided by the ATE vendor, are normally required. No matter how well correlated the ATE emulation is with the actual ATE hardware, some additional debugging will always be required.
In most implementations, Dantes is used as a front-end tool, primarily to generate test code.3,4,5 In this situation, ATE setup conditions are added, and code optimized and further debugged by using the tester-specific software environment. But the ATE-specific debug tools usually alter the program forever, making it almost impossible to perform more off-line debug in the simulation environment.
“To be truly effective, a design-to-test tool such as Dantes must take setup data not only from the simulation environment but also from the tester hardware,” said Ken Lanier, Marketing Manager for the Mixed-Signal Division at LTX. “In addition, a tool like Dantes must become the debug tool on the tester. You should be able to move a test program partially debugged on the tester back into the Dantes simulation environment.
To achieve this functionality, LTX has worked with Cadence to integrate the LTX Synchro Device Tool into the Dantes Virtual Test environment. “As a result, the designer, test engineer and product engineer all deal with the same set of tools operating off the same data base,” Mr. Lanier concluded.
But LTX is not alone in pursuing this approach. Teradyne has also worked with Cadence to produce a two-way data exchange implementation. Called IMAGE ExChangeä , it links the Teradyne tester software IMAGEä with Dantes (Figure 1).
When IMAGE is running on a stand-alone workstation, the IMAGE test program loader automatically links and loads the IMAGE tester-simulator software package. However, the standard IMAGE software does not simulate the application hardware or the DUT. That is where Dantes and IMAGE ExChangecome in.
IMAGE ExChange not only provides the linkage and required data conversion between IMAGE and Dantes, but also furnishes a master time base. IMAGE ExChange describes what is happening to the tester instrumentation and when those changes happen during the program execution.7 Dantes accepts the stimuli and returns responses from its simulator, using the device and instrumentation models to mimic the performance of an actual device on the tester.
Results From a Pilot Project
A paper presented at the 1995 International Test Conference reported the results of a pilot project undertaken by Teradyne and Texas Instrument to determine the efficacy of implementing a two-way design-to-test methodology.8 The device chosen for the test performed a Codec-like function. It was approximately 60% digital in nature and had approximately 100 pins.
The project was a success for both the design and test groups:
The cycle time was reduced so that four to six weeks of the usual post-silicon development effort was shifted to pre-silicon.
Approximately two to three hours spent on the simulator saved one hour of ATE usage during program development.
Multiple flaws were found in the device design pre-silicon.
Multiple errors were found in the test program prior to device existence.
The portions of the test program that were verified via simulation contained almost no bugs when exercised on the ATE.
In further analysis of the project, the team made these observations:
While linking the design and test environments did reduce cycle time, it did not reduce the amount of time a test engineer must spend debugging a test program. In fact, it increased this time.
The process was helpful not only in program debug, but also in device design.
Becoming familiar with the model of the device was an effective way to understand its functions.
Not every design/test group will need complete design-to-test methodology. However, implementing a two-way simulation/emulation design-to-test process will often be well worth the effort because it benefits both the design and test development.8
1. Norton, E.B., “New Approaches to DSP Software Reduce Test-Program Development,” Evaluation Engineering, July 1995, pp. 37-39.
2. Bateman, S.C., and Kao, W.H., “Simulation of an Integrated Design and Test Environment for Mixed-Signal,” Proceedings of the International Test Conference 1992, pp. 405-411.
3. Kao, W. and Hasebe, K., “Simulation of Tester Environment Improves Design to Test Link for Mixed Signal IC’s,” Proceedings of the ATE & Instrumentation Conference West 1991, pp. 109-116.
4. Kao, W. and Boydston, T., “Automatic Test Program Generation for Mixed Signal ICs via Design to Test Link,” Proceedings of the International Test Conference 1992, pp. 860-865.
5. Austin, T., “Creating a Mixed-Signal Simulation Capability for Concurrent IC Design and Test Program Development,” Proceedings of the International Test Conference 1993, pp. 125-132.
6. Austin, T., et al, “Faster Mixed-Signal Development Using CAD to Model IC, Package and Test System,” IEEE 1994 International Conference on Electronics, Circuits and Systems.
7. Austin, T., et al, “IMAGE ExChange: An Enabling Technology for Virtual Test,” Teradyne, Inc.
8. Bullock, S., “Report on a Pilot Project Successfully Implementing a Design-to-Test Methodology,” Proceedings of the International Test Conference 1995.
Mixed-Signal ATE Products
System Tests VLSI Digital,
The Duo™ System tests high-performance VLSI digital and combined digital/mixed-signal devices, including multimedia, digital video and digitized audio subsystems. Duo supplies 100-MHz I/O on 512 pins in conjunction with a matched differential mixed-signal DSP instrumentation cluster. It accommodates the embedded, digitized analog functions that characterize advance mass storage, graphics subsystems, local and wide area networks, and digitized audio while providing multisite test capabilities. Configurations range from 32 to 512 digital pins and 4 to 128 DSP analog pins. Credence Systems Corp., (510) 657-7400.
Mixed-Signal Test System
Two new capabilities, the Analog Pin Unit (APU) and the Medium Power Unit V/I (MPU), expand the performance range of the ETS-500D Mixed-Signal Test System. The APU provides general-purpose force/measure capability on a per-pin basis for up to 96 pins with a range of +30 V/+100 mA. Each group of eight channels includes a separate 16-bit AWG and digitizer. The MPU is a four-quadrant V/I that can force voltage up to 120 V and current to 40 A. It also generates arbitrary power waveforms and offers a built-in 16-bit digitizer. Eagle Test Systems, Inc., (708) 367-8282.
Mixed-Signal Tester Features
Enhanced Digital Capabilities
The HP 9494 and HP 9495 Mixed-Signal Test Systems address characterization and production test demands for digitally intensive mixed-signal devices with up to 128 and 256 pins, respectively. The systems provide 16 sets of per-pin edge timing on the fly, a 64-MHz digital data rate and 4-M vector memory. They accommodate mixed-signal, large-scale ICs used for digital cellular and cordless phones, hard disk drives and integrated signal-processing applications. Earlier HP 9490 Series systems are field upgradable. Hewlett-Packard Co., (800) 452-4844.
Test Capability Extended For
The Low Noise Option allows IMS test stations to characterize and test very-high-resolution devices, such as 16-, 18- and 20-bit converters and telecom interfaces. A mixed-signal test station with this option features a -140-dB noise floor, good analog and digital separation for low crosstalk and signal isolation. System noise is minimized with a custom power conditioner, opto-isolation of GPIB and Ethernet links and careful device-fixture design. Integrated Measurements Systems, Inc., (800) 879-7117.
The Delta/ST VLSI Test System provides functional test capabilities at 50/100/150 MHz for testing high-performance audio, video, graphics and communications signals on digitally intensive ICs. Digital testing is done through the HiFlex digital timing architecture combined with the Trillium Dual-Pattern Subsystem. Six timing edges, 32 timesets per pin, and more than 32,000 global waveform combinations are provided. Data pattern memory is configurable for 1, 2, 4 or 8M vectors along with a 16k control pattern memory. LTX Corp., (617) 461-1000.
Mixed-Signal System Features
Visual User Environment
The M3610 Mixed-Signal Test System features a noise floor below -120 dB. It can be configured with a serial data processor, four-quadrant high-power V/I sources and up to four DSP CPUs running simultaneously. The mixed-signal pin electronics, located at the test head, preserve signal quality. Graphical software tools, including analog and digital waveform editors, reduce application effort, programming and test time. SZ Testsysteme, (408) 744-0793.
Features Parallel Test
The modular A565 Advanced Mixed-Signal Test System is designed for testing linear-with-digital and integrated mixed-signal devices as used in peripheral, telecommunications, wireless and automotive applications. It features new instrumentation for parallel test and a 30% footprint reduction. Utilizing the digital technology from the A585/A575, the A565 guarantees edge-placement accuracy that reduces test guard bands, improving device yields. IMAGE software, the interactive menu-assisted graphics environment that accelerates programming efforts, allows development and debugging of test programs off-line. Teradyne, Inc., (617) 482-2700.
Copyright 1995 Nelson Publishing Inc.