Using Accelerated Testing Techniques to Improve Product Quality

Most companies are constantly looking for ways to improve product quality, and Sequent Computer Systems is no exception. Recently, the company compared traditional functional burn-in testing to a structured accelerated life test combined with environmental stress screening and found a much more efficient process that enhances quality as well as reduces test cycle time.

The products used to compare the processes were two generations of Sequent’s Pentium-based processor boards. Surface-mount devices make up the majority of the components on the printed circuit assemblies. Each assembly had approximately 2,000 fine-pitch solder joints and approximately 11,000 total solder joints. The assemblies were double-sided with passive devices mounted on the secondary side. For this investigation, the first product is referred to as Product 1 (no ESS) and the second-generation product is Product 2 (with ESS).

In the Product 1 test process, the boards were assembled, ICT was completed, and FT and FB were performed. The final test was completed in an ST, where the product was configured to customer order and tested.

FT used a diagnostic test suite that took approximately eight hours to perform in an ambient environment at nominal voltages. FB was conducted in a modified Sequent system capable of temperature variations between +25°C to +45°C and voltage variations of 5%.

FB used the same suite of diagnostics that was used in the previous FT step along with OS level test suites. Duration for FB was seven days. The final test step was ST, completed in an ambient environment at nominal temperatures. The system was configured per customer specifications and testing was performed for an additional 24 hours.

Product 1 had an ST failure rate of 7%. The main defect in the ST test was unsoldered fine-pitch parts. The combined failure rate in FT and FB was more than 25%. Most failure mechanisms were related to component failures and assembly defects.

Accelerated Life Testing

With the start of a new product line, we decided to verify the robustness of the new design and its associated assembly processes. We chose an ALT that used a combination of temperature, voltage and vibration to weed out design marginality and assembly-process shortcomings. The goal of ALT is to ignore the product specifications and find the actual operational and destruct limits of the product.

We purchased an ESS chamber that provided the thermal and vibration capabilities we needed. We developed a variable output power supply and a custom chassis to handle the vibration levels we would reach.

A Sequent SE 20 system was modified to fit into the chamber. The peripherals and power supplies were externally cabled to the fixturing inside the chamber. Air ducting was created so the airflow across all areas of the board and in all slots of the chassis was uniform.

The temperature was controlled by a PC-based system which monitored a thermocouple that measured the temperature of the air exiting the test fixture. Vibration was also controlled by the same PC-based system, using an accelerometer mounted to the bottom of the vibration table.

During this ALT, the boards had three accelerometers and five thermocouples strategically attached to them to do additional characterization. This characterization information was used to determine whether we were violating the destruct limits of the individual components on the boards.

Environmental Stress Screening

An ESS profile was based on the ALT results and a Proof of Screen was performed. We typically derated the temperature and vibration extremes during ALT by 25% to compile our ESS profile temperature and vibration levels. Once the ESS levels were established, we completed a Proof of Screen to verify that good product was not damaged by the ESS profile.

To successfully complete the Proof of Screen, we tested known-good product through the ESS profile 10 times. No flaws should be induced during Proof of Screen and there should be no intermittent failures due to testing too close to the operational limits of the product.

The initial screen contained temperature margining and 2 grms vibration. The vibration used in both the ALT and the ESS was a multi-axis or six-degrees-of-freedom impact-type broadband random vibration. This vibration was created by pneumatic hammers mounted to the bottom side of a spring-suspended rigid shaker table.

The new test process (Product 2) allowed us to decrease the FT time to approximately two hours. Our analysis showed that we were catching stuck-at faults in the first two hours of test, so the remaining six hours were buying us no additional coverage.

An ESS process step was inserted in front of FB, and FB was reduced from seven days to two. The FB reduction was based upon empirical data we collected while testing a large sample population of our standard product. The combination of temperature and vibration testing completed during ESS eliminated the need for FB testing beyond two days. Additionally, temperature margining was removed from the FB (Figure 1).

The ESS setup used a combination temperature and vibration chamber with four modified SE 20 systems. These systems were mounted two on each side of the chamber in a stacked configuration. Each system had airflow ducted directly to it and the average airflow across the boards was 800 CFM. All external peripherals and power supplies were cabled to the chamber (Figure 2).

During ESS, the boards were powered and running monitored diagnostics at all times. Any failure resulted in the assembly going into board-level debug for detailed failure analysis and repair. Once the product was repaired, it was required to restart and pass the entire test process.

Early monitoring of the ESS process was crucial for screen enhancement. Any products that failed in FB were held for further investigation.

During this investigation, there were 10 failing boards that would not fail consistently in the ESS process. All 10 failing boards had visually confirmed unsoldered pins. These boards were run through a series of experiments using different vibration and temperature levels to try to uncover the unsoldered pins.

We were unable to get 100% correlation at temperature or at steady-state vibration. We did discover that if the vibration magnitude level was constantly changing, all 10 boards would fail repeatably.

We changed to modulated vibration during the diagnostic portion of the test screen to capture these types of assembly failures. Modulated vibration involved changing the input vibration levels between 8 grms and 20 grms every 15 seconds in 4-grms steps.

Since this change, the only major assembly defects not detected in ESS were partially soldered SMT backside resistors and capacitors glued to the board. This problem was resolved by changing the assembly process for backside components (Figure 3).

Product 2 had an ST failure rate of 2.2%. This failure rate was a 3X improvement over Product 1 with a test process that was 3X shorter (Figure 4).

Conclusion

Utilizing ALT and ESS has enhanced the design process while improving the detection of product failures and reducing production test-cycle time. For example, when we implemented these processes on the SE20 and SE60 products, the result was a reduced system failure rate.

Remember this is not a “cure all” and any failures found in this process should have root-cause analysis and closed-loop corrective action performed. We also recommend that a periodic ALT be completed on a sample basis to determine whether there have been any process shifts that may adversely affect the quality of the outgoing product.

References

1. Hobbs, G. K. , “HALT & HASS,” Course Outline Material, 1993.

2. Hopf, A. M., “HALT & HASS at Array Technology,” Proceedings of the IES, 1993, pp. 147-145.

3. McLean, H., “Highly Accelerated Stressing of Products With Very Low Failure Rates,” Proceedings of the IES, 1992, pp. 443-450.

4. McKenney, K., “Test Cycle Time Reduction and Improved Quality By Using Accelerated Testing Techniques,” Proceedings of the IES, 1995, pp. 72-79.

Author’s Note

This article was started by Kevin McKenney, who passed away on Oct. 3, 1995. I completed it in memory of his contributions to Sequent’s success and to my own personal development. He will be missed.

About the Authors

Kevin McKenney was the Test Engineering Manager at Sequent Computer Systems. He worked in the electronics test field for 13 years, the last 2 as the project lead for the implementation of ALT and ESS testing at the company.

Jerry Peasley is a Test Engineer at Sequent. He has worked in test engineering, component engineering new-product development and field service during his 15 years in the electronics industry. Sequent Computer Systems, 15450 S.W. Koll Parkway, Beaverton, OR 97006, (503) 578-4470.

Legend

ALT Accelerated Life Test

ESS Environmental Stress Screening

OS Operating System

ICT In-Circuit Test

FT Functional Test

FB Functional Burn-in

ST Systems Configuration

March 1996