The recent semiconductor industry slowdown allowed some ATE manufacturers to focus on the upcoming release of new, high-performance, flash-memory tester solutions. These ×16 memory testers now are challenging the probe-card and interface suppliers to exceed their current capabilities so customers can fully use their new equipment at wafer sort.
New rules and procedures are evolving for the design and construction of multi-DUT electromechanical interface products. Some of the changes are subtle, but others have great effects on the appearance and the performance and pricing of the interface (Figure 1).
Previously, a customer selected different suppliers for load boards, pogo stacks, probe cards, and docking. To continue to do so will greatly increase the risk that mismatched components will cause the performance of the interface to limit test-system performance.
Individual component-design advancement is a result of overall system-design evolution and the need for better electrical performance. The electrical-performance specification for the interface system drives the specs on any one part.
If a single qualified source is used to design and build the probe card and interface, the system should not suffer from mismatched source and termination resistance, impedance, or line widths, that cause reflections, parasitic capacitance and inductance, line losses, and crosstalk. This creates a better environment for minimizing propagation delay and distortion of edge rates.
The most notable flash-memory interface changes have been to the probe card (Figure 2). More epoxy-ring, cantilever-type probe cards are testing flash products than any other type of probe card. With ×16 testing, this does not necessarily have to change—unless, of course, the wafer process includes controlled, collapsed chip connection technology. In that case, a vertical probe is recommended.
Most arrays will continue to be referred to as “one by…” or “two by…”. That is, they will have one or two die maximum in at least one direction.
What will change is the number of qualified suppliers to build these cards. The size and pitch of perimeter-placed pads are continually decreasing, and it is not uncommon to see 50-µm pads with a 60-µm to 65-µm pitch.
No longer are bond pads placed on just one or two sides of the die. This necessitates bringing the probes to the DUT on many different tiers or planes.
Also complicating the process is the increasing need to reduce bond-pad side and pitch. This requires probe cards to increase the density of the probe-tip needles while reducing the tip size and the amount of overdrive.
Now more than ever before, it is critical to planarize the large, dense, ×16 arrays within smaller tolerance ranges. The complicated process and tooling necessary to accomplish this will be overwhelming for some of the smaller probe-card shops.
The flash-interface probe-card layout depends first upon the array. A probe card supplier determines the largest possible die that can be verified with that tester. A good conservative practice assumes that all pin and DUT resources will be used.
The array should be laid out in every conceivable fashion to identify the worst case, that which requires the most space. This procedure helps the probe-card designer to lay out the tester sites, trace and component-mounting areas, and pogo lands so as not to encroach on the array.
Next, the tester-site probe lands are laid out, and a sufficient area is kept as a keep-out zone for components and traces. There is no specific rule for how much space to reserve for the keep-out zone; but generally speaking, more is better. This fans out the pogo array, simplifying the signal routing that helps reduce the layer count and the cost of the board.
Laying out the pogo array should not be done initially on the probe card because the pattern on the card actually can be condensed from what the pogo stack allows. It is better to design the pogo array on the pogo stack, then jump back to complete the probe-card layout.
Figure 3 shows the different types of 50-W transmission lines that can be used for the pogo array. The two-wire array places a ground return in very close proximity to the signal. Any variation in this distance causes degradation in the signal.
The five-wire array has a signal pin surrounded by four grounds. It performs well up to the 5-GHz to 6-GHz range, but its space utilization is slightly worse than the co-planar array.
The five-wire array has friendlier spacing for PC designers and slightly better crosstalk and impedance control than the co-planar array. Unfortunately, because of space constraints, this type of transmission line in high-density multi-DUT applications is very limited.
The three-wire, or co-planar, array probably is the most common. In this model, each signal is bordered by two ground pins. This type of transmission line can be used in applications requiring up to 5-GHz bandwidth. It is more cost-effective than all of the other transmission lines except the two-wire array.
On the downside, it needs more real estate than the two-wire array. For four signal pins, nine pogo pins are required. This transmission line is the most logical cost/performance solution for flash-memory interfaces. After constructing the pogo pin array, it can be transferred onto the probe card.
The PCB portion of the probe card can be routed using a microstrip line, embedded microstrip, stripline, dual stripline, asymmetric stripline, or any combination of these. The performance requirements of a flash tester leave the choices pretty much open since the microstrip can be designed to perform in the 2-GHz to 3-GHz range. The advantages of the microstrip line for flash are the relative ease in adding matching resistors or other components to the signal path and lower board cost.
Providing structural integrity to the probe card is taking on new meaning with the high-pin-count memory testers. There is virtually no way to eliminate board deflection. With array openings of five to six inches and more, it is becoming commonplace on cantilever-type probe cards to provide a stiffener around the perimeter of the board. It also is possible to mount a top-side metal support that attaches as close to the array as possible. This is a common-sense solution if the interface supplier and customer are prepared to spend extra time to characterize thermal-expansion mismatches due to materials.
Modeling the deflection with a finite-element analysis package is a good, conservative step in the design process. This takes as much expertise as it does time, but it is worth the effort when you can characterize the impact of deflection in position and height of probes around a large rectangular array.
Depending on the application, the pogo stack can be a solitary piece. If no test head exists, the pogo stack can be mated to a connector board. Coax cables are plugged into the connector board on one end and into the tester on the other.
Give special care to the type of cable and connectors used. Many flash products are sensitive to capacitance. Using low-capacitance cables with shielded and quiet connectors is a bit more pricey but worth the added expense.
With the direct-dock type of flash interface, the load board probably will use the same type of transmission line as the probe card. Again, microstrip is recommended because of its flexibility for component mounting. Adequate space must be provided between the pogo pattern and the tester pin-out pattern for routing traces as well as mounting components.
Conclusions
Designing the tester-to-wafer-prober interface is only slightly more than half the battle in the greater picture of flash multi-DUT interfacing. Characterizing and tweaking more than 1,000 probes at the planarization station are getting tougher and tougher.
Each different probe-card type has a tooling fixture, or motherboard, that allows it to interface to the planarization station. This motherboard is supposed to emulate the tester-to-wafer prober interface. That means putting the same forces on the probe card that the pogo pins in the interface do and providing the same materials, and thickness thereof, for structural support. This allows the probes to be planarized to windows or ranges of 0.00025″ to 0.0005″, depending on the user.
Although the initial expense would be higher, this question has to be asked: Wouldn’t it make more sense to design tester interfaces that stay married to the probe card on both the prober and the metrology tool?
About the Author
Jim Anderson is the director of marketing for interface products at Cerprobe. He has 12 years of experience in the semiconductor industry including engineering manager positions in charge of prober, interface, and probe-card changer development. Mr. Anderson currently serves as chair for the SEMI Prober Standards Task Force. Cerprobe, 600 S. Rockford Dr., Tempe, AZ 85281, (602) 967-7885.
Copyright 1997 Nelson Publishing Inc.
September 1997
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