Driven by today’s need to increase system performance, manufacturers of analog I/O for the VXI/VME bus are incorporating direct memory access (DMA) to manage data transfers. DMA is a method of exchanging data between system memory and peripheral devices or system I/O under control of a device other than the system CPU.
Originally, it was used in a computer as an interface between memory and peripheral devices and then incorporated into system I/O components. Now, DMA is being used to increase VXI test system speed and efficiency.
The ability of automated test systems to perform more tests in less time translates directly into dollars saved. VXI-based test systems have greatly contributed to satisfying this need; however, the inherent advantages of VXI can be fully realized only if the system components do not present limitations.
One area that can present a bottleneck to VXI test system performance is a dependence on the system controller’s CPU to manage VXI instrument functionality. A way to decrease this dependenceis to free the system’s CPU from managing data transfer tasks.
The CPU can then perform other tasks such as data analysis and control of other system resources while data transfers are managed by a DMA controller remote to the system CPU (Figure 1). This capability can result in substantially reduced test time.
In a typical DMA implementation, a digitizer instrument acquires data and then transfers the data to system memory. DMA also can transfer data from memory to an instrument, such as a waveform generator, or anytime data must be moved into or out of memory.
In a digitizer, the data word produced by each A/D conversion is loaded into a first-in first-out (FIFO). When the FIFO becomes half full, the on-board DMA controller requests use of the VME/VXI bus.
When granted the bus by the system controller, the DMA controller becomes the bus master. At this time, the system controller is relieved of the responsibility of managing bus activity, and bus control for data transfers is given to the DMA controller.
Then the contents of the FIFO are transferred at a high rate into system memory. When the FIFO is totally empty, the DMA controller releases the bus so that another VXI instrument or the system controller can use it. When the FIFO becomes half full again, the cycle repeats. As a result, bursts of data are transferred to system memory during data acquisition. The period of time between DMA cycles when the bus is available to other devices, is determined by:
The period of time to half fill the FIFO, determined by the rate at which data is acquired (aggregate sampling rate).
The period of time between bus request (FIFO half full) and bus grant, determined by other VXI instruments that might be a bus master at the time the DMA controller requests the bus. Other devices must relinquish the bus before the DMA controller can be granted the bus. During this time, the FIFO continues to accumulate data words so that it fills beyond half capacity.
The period of time required to empty the FIFO by transferring data from the FIFO to system memory via DMA. This is determined by the total number of data words that accumulated in the FIFO prior to the start of the DMA data transfer, the DMA controller’s transfer rate, and memory-write cycle time.
The address to which the data is sent is one of the start-up parameters of the DMA controller. It usually is contained in a table downloaded to the DMA controller before data transfers start. This table is commonly referred to as the chain table.
A chain table also includes the number of data words (data-buffer size) to be transferred to memory. Upon transfer of the specified number of data words, an interrupt or other flag typically is generated, and one of these options may be implemented via the chain table:
The buffer may be written over, starting at the originally specified address.
A new buffer with a new starting address may be written seamlessly. This allows simultaneously writing one buffer while the previously written buffer’s data set is available for application-specific functions. This process also can be used if more than two buffers are desired.
DMA activity is suspended.
DMA technology is available today in VXI instruments, and some VXI system controllers also implement DMA. However, embedding DMA control directly within an instrument produces the highest performance potential because the DMA controller does not have to share its functionality with multiple devices. DMA control within the instrument also allows the system CPU maximum freedom to handle other tasks.
Management of data transfers within a VXI system can place considerable burden on the system CPU. Unburdening the CPU via DMA increases VXI system speed, efficiency, and resource utilization.
About the Author
Andy Fagan is an application engineer at Analogic’s Measurement and Control Division. Before joining the company in 1988, he held various engineering and management positions. Analogic, 8 Centennial Dr., Peabody, MA 01960, (978) 977-3000.
Copyright 1998 Nelson Publishing Inc.