New Technology Offers a Smoother Route to Microcontroller Test

Recent years have seen an explosion in the microcontroller marketplace. The devices now are used in a wide range of end products, from toys to electronics and automobiles.

Virtually any product is a candidate for a microcontroller. Some microcontrollers are relatively simple, such as a chip for a smart money card. Others are highly complex, such as controllers for video games or personal digital assistants.

But whether microcontrollers cost less than $0.50 or several dollars, manufacturers are being squeezed by the same pressures: to improve functionality while decreasing costs. Greatly increasing this pressure is the prediction that the demand for microcontrollers will double by the year 2000.

Market forces are demanding constantly lower prices and greater functionality so that end products will have a competitive advantage. Technically, however, this creates serious problems for microcontroller manufacturers who must incorporate processors, memory, A/D converters, and an increasing array of components—all of which complicate the production and testing process (Figure 1).

Great strides have been made in the design and manufacture of this new breed of highly integrated chips. But the capability of test systems to keep up with cost, complexity, and production demands has lagged behind.

Testing Devices Faster and Cheaper

No doubt, testing has become a primary obstacle to reducing the microcontroller cost. Indeed, the test process, including development and production testing, can account for as much as 10% to 25% of a microcontroller’s total cost. This percentage actually has grown in recent years because, while the cost of microcontrollers has declined dramatically, the cost of testing has not.

Any savings that can be achieved in testing will have a dramatic impact on the total cost of the microcontroller. Many test managers in the microcontroller industry have been directed by management to reduce test costs by as much as 50%.

However, reducing test cost is especially difficult because of the growing complexity of the devices. While today’s process technology makes it relatively easy to bolt on a Meg of memory and 12-bit A/Ds to create a new microcontroller, there is nothing easy about testing that device, especially with the economic constraints faced by most manufacturers.

Many variations within a family of microcontrollers also create a test-program maintenance nightmare. The different combinations proliferate hundreds of slightly different test programs that have to be managed on a lot-by-lot basis in production.

Nevertheless, there are several ways to reduce test time and cost using the latest technology. By looking closely at microcontroller test requirements and integrating technologies from VLSI, mixed-signal, and memory testers, it is possible to create a test system that handles complex test requirements while meeting the throughput and cost demands of the marketplace.

Easing the Burdens of Complexity

Sophisticated Per-Pin Timing Systems

The growing complexity of today’s microcontrollers leads directly to the need for a test system with a flexible and sophisticated digital timing architecture. Combining ROM, SRAM, and flash memory on a single device, and accessing them all through the same data port requires a test pattern with as many as 20 or 30 unique edge sets.

Modern VLSI timing systems allow you to define edge sets, which include timing and format information, for each digital pin. These local edge sets then can be changed on the fly within a pattern on a cycle-by-cycle basis.

Testers with deep and flexible timing systems allow you to create these complex microcontroller patterns automatically from CAD simulation data. Older architectures with more limited timing require careful handcrafting of patterns, which increases the time and complexity of test-program creation and, even worse, can compromise fault coverage.

Modular Test Programs

Tester software also can ease the burden of complexity by helping you manage the creation and maintenance of a multitude of test programs and variations. Like the devices themselves, microcontroller test programs can be created in modular fashion. The tester software must allow you to create and modify programs by entering only device data. The data must be organized in a modular fashion, such as a simple spreadsheet of device specifications or device pin assignments.

With these building blocks of data, you can maintain many variations of the same test in a single test program. Then the specific specs, timing, levels, and test flow for a derivative part can be defined at run time. These features centralize and streamline the creation and maintenance of test programs and give production flexibility for tightly controlling the test flow on a lot-by-lot basis.

Throughput at Device Speed

The closer the test runs at device speed, rather than at tester speed, the better. A close examination of traditional test-system architecture reveals that much of the test-time overhead relates to characteristics of the tester and how it interacts with the device—not in the test per se. What is worse, this overhead often is amplified in parallel test environments (Figure 2).

Pattern-Controlled vs Computer-Controlled Instruments

One example of this problem is the way that commands are communicated to instruments, resulting in excessive time consumed by the tester as opposed to the test itself. This can be illustrated by a simple example. Suppose you need to run a linearity test of the A/D converter in a microcontroller, and you want to test eight devices in parallel. In a traditional microcontroller tester, you would instruct the tester to generate a separate command to each device for each voltage level. If you assume 1,024 samples per device and a computer I/O overhead of 100 µs for each command, you have an additional 800 ms of pure overhead.

In this scenario, virtually all of the test time is consumed by the tester and the overhead that results from the system architecture. However, most of that overhead can be eliminated by using digital patterns that can simultaneously control all instruments (assuming an instrument-per-site architecture). Pattern-controlled instrumentation frequently is used in high-end, mixed-signal testing and can be applied very effectively to microcontrollers.

If we substitute pattern-controlled instruments in the example, we arrive at a very different result: The entire system overhead for the linearity test is just microseconds, the time required for the system to start the pattern generator. The test time has been reduced very nearly to the theoretical limit—the device’s converter settling speed.

Per-Site Programming and Per-Site Instruments

Traditionally, VLSI test systems have been programmed from the computer on a per-channel basis. While this works well enough when testing a small number of devices, it results in decreasing throughput returns as you increase the device count. In other words, the more devices you try to test in parallel, the more your throughput gains are diminished, defeating the purpose of the parallel test.

This is because per-channel programming requires a separate set of software commands for each channel. As the devices-under-test multiply, so do the commands executed by the test computer, which must talk to each digital pin or test instrument in serial fashion.

It’s not unusual for this computer-to-tester communications to increase the total test time from 20% to 35% every time the number of parallel test sites is doubled. With a 35% test-time penalty, doubling the number of sites would increase the total throughput of the system only by about 50%.

A more suitable approach for parallel testing is per-site programming. Per-site architecture commonly is used for testing memory because it allows you to use site registers in the hardware to set up and control multiple instruments with a single command. With this architecture, the computer-to-tester overhead can be reduced to 1% to 2% of the single-site test time. With almost no test-time penalty, increasing parallelism becomes the most efficient and economic solution for increasing throughput.

In addition to per-site programming, having separate instruments for each device is critical. Anything less requires significant portions of the test flow to be run serially through each device.

If all devices in a given run must be tested synchronously, the test time will be equal to the time required for the slowest device or, even worse, equal to the sum of the slowest tests across all devices. Asynchronous testing, on the other hand, allows much greater flexibility because the tester can perform functional and memory-pattern testing asynchronously, further optimizing parallel test throughput.

For each device, a pattern controller can react independently to failures and execute match loops and memory programming algorithms on a cell-by-cell basis. Asynchronous pattern generators are advantageous for flash memory testing because individual memory cells which program faster or erase faster do not have to wait for the slower cells (Figure 3). It also means that no flash memories are over-programmed. Again, parallel test times improve.

Reducing Test Time

In theory, applying technology from memory, VLSI, and mixed-signal testers to microcontroller testing can improve production throughput. When we move from theory to the reality of microcontroller testing, the production gains become even more apparent. The reason is simple. The majority of test time is related to two devices that are found in many of today’s microcontrollers: memory and A/D converters.

The technologies discussed in this article have the greatest impact on these two types of devices. Asynchronous timing directly improves flash memory test times, and pattern-controlled instrumentation does the same for A/D test times. By improving the test throughput of these two devices alone, not to mention the myriad of other devices in a typical microcontroller, manufacturers can achieve dramatic improvements in cost and throughput.

Integration Technology

Granted, high-end testing technology can be applied to the microcontroller challenge. But can it be done economically? No microcontroller manufacturer can afford to buy three different high-end systems for memory, VLSI, and analog components.

Solving this problem requires that test-system manufacturers rethink the way test systems are designed. By increasing the level of integration in a test system, it is possible to incorporate an instrument-per-site architecture into a microcontroller tester that fits the economic demands of the industry.

This integration can significantly reduce the size of the test system, resulting in a complete microcontroller tester that fits in the space previously required for the test head alone. This drastic reduction in size results in a corresponding decrease in manufacturing costs, creates more flexibility in production, and frees up valuable real estate on the factory floor for other critical operations. A smaller tester also reduces the cost of test ownership, since it requires less power, less maintenance, and less cooling.

Where We Stand Today

Microcontroller manufacturers being squeezed by market pressures have reason to be optimistic. Not only is it possible to reduce test costs, but it also is beginning to happen today.

About the Author

Ian Lawee is a product manager at Teradyne’s new Integra Test Division. Mr. Lawee earned a bachelor’s degree in computer science from the University of Pennsylvania and master’s degrees in electrical engineering and management from MIT. Teradyne, Integra Test Division, 9 Crosby Dr., Bedford, MA 01730, (781) 275-1817, e-mail: [email protected].

April 1998