Overcoming Round-Trip Delay Obstacles

As IC manufacturers continue to increase the operating frequencies of their devices, tester manufacturers have to speed up their pin electronics to keep pace. Today, several manufacturers offer systems that can test at 400/800-MHz (400-MHz base rate, 800-MHz multiplexed). Indeed, these testers can generate test vectors and compare device output data at these speeds.

The problem isn’t in generating test vectors or measuring outputs. The problem is doing both on the same pin, at the device I/O switching speeds.

Testing I/O pins at-speed becomes a problem in physics. As device-clock speeds increase, the time it takes for the signal to travel from the driver to the device-under-test (DUT) and back to the comparator becomes a factor. This time is called round-trip delay (RTD) and is highly dependent on the test station and the designs of the pin electronics and device interface board.

As shown in Figure 1, when calculating the RTD, the entire signal path of a test system must be considered, including from the:

Driver to the pogo pin connecting to the test fixture (Segment A).

Top of the pogo pin to the test socket and back to the pogo pin (Segments B and C).

Pogo pin to the comparator (Segment D).

Test-system manufacturers define RTD in many ways. In my opinion, the definition of RTD should be the time required for a signal to travel from the driver to the center of the DUT board and back to the comparator.

Different test stations have different physical geometries—there are round test stations and there are rectangular ones. The RTD specification must represent the longest electrical signal path for any channel in any test station, regardless of the physical design.

In conjunction with the timing parameters of output tristate time (Txz) and setup time (Tsu), RTD limits the maximum I/O frequency at which a device can be tested using a single channel path. The relationship is very simple. The minimum clock period for a tester cycle is:

Minimum Clock Period ³ Txz + Tsu + RTD

For example, when Txz, Tsu, and RTD are all 1 ns, the minimum period for a tester cycle is 3 ns. This translates to a maximum I/O test frequency of 333.3 MHz.

Unfortunately, 1 ns is a very optimistic number. Actual values are higher for RTD as well as for Txz and Tsu. For example, one ATE manufacturer specifies a 3-ns RTD for its 400/800-MHz tester; another specifies an RTD of 6 ns.

Assuming a Txz and Tsu of 1 ns, when the RTD is 3 ns, the maximum frequency at which you can test I/O pins is 200 MHz. When the RTD is 6 ns, the maximum I/O test frequency is 125 MHz.

Dead Cycles

One way to deal with this obstacle is to include dead cycles in the test program. During a dead cycle, there is no activity at the DUT I/O pin. By inserting a dead cycle at the appropriate points, you can increase the maximum test frequency because the time Txz + Tsu + RTD now equals two clock periods. For a 1-ns RTD, the maximum test frequency now becomes 667 MHz. For a 3-ns RTD, it is 400 MHz; and for a 6-ns RTD, it is 250 MHz.

But there are some drawbacks. When you insert dead cycles, you are operating the device that is not representative of the way it actually will operate in a circuit. The device input-to-output and output-to-input transition time cannot be tested. This could affect the validity of the testing.

Also, while you can perform a no-operation instruction or dead cycle on an input, you cannot control what happens on the outputs. All you can do is ignore output data. In fact, you could be ignoring output data that may contain failures, decreasing or compromising the test coverage.

And the devices you have to test may not allow dead cycles. Many devices, including those with dynamic output holding states, will not work properly with dead cycles. This limits the capability of the system to adequately test these devices.

Making Testers Fly

Another method used for high-speed testing is fly-by. As shown in Figure 2, fly-by testing uses two channels to test each DUT I/O pin. One channel drives the DUT I/O pin, while the comparator of the other senses the DUT output. In effect, a transmission line is formed between the driver and comparator, with the device I/O pin at the center point.

Using fly-by requires both ends of the transmission line to be properly terminated, most often with 50 W to a termination voltage (Vt) to eliminate unwanted reflections. This technique eliminates the test system’s contribution to RTD. The RTD that remains is attributable only to the test socket and device package. As a result, fly-by eliminates RTD as an obstacle to high-speed I/O testing. For this technique to work, the driver must generate the proper Vt level during the compare cycle.

There is one major drawback: two channels must be used for each DUT I/O pin. Consequently, fly-by testing increases the cost per channel for each I/O pin that must be tested.

There also are some device drive issues. Using two channels per DUT I/O pin lowers the impedance of the device I/O pin to 25

W. This requires the device to drive a lower impedance than the typical 50-W tester channel transmission line.

The New Architecture

A new multipin architecture delivers the benefits of fly-by testing at a considerably lower cost. It has one trilevel driver and two comparators per channel as shown in Figure 3. By providing separate (or split) I and O connections, this design supplies fly-by test capability per channel without losing channels. The trilevel driver allows easy insertion of the Vt load during the DUT drive cycle. Only one channel tests each device I/O pin at-speed.

As a result, the cost per DUT I/O pin is less than that of fly-by with traditional two-channel techniques. This is especially important because both the speed and the pin-count are increasing significantly in today’s new devices.

Conclusions

The semiconductor world needs new system architectures that keep pace with the demand for economic test needs of today’s devices. As devices pass the 250-MHz range, RTD becomes a major physical barrier that some current systems cannot accommodate. New designs with a multipin architecture provide solutions to meet the performance and economic needs of next-generation high-speed, high pin-count devices.

About the Author

Jerry Katz is the manager of test engineering at the Advantest America R&D Center. He began his career in the field of semiconductor test 28 years ago at Fairchild. Mr. Katz is a graduate of the University of Santa Clara with a degree in electrical engineering. Advantest America, R&D Center, 3201 Scott Blvd., Santa Clara, CA 95054, (408) 727-2222.

May 1998