Multisite Systems Lower Test Costs for Telecom Devices

Test technology usually is introduced because advances in IC technology have increased a chip’s speed or functionality to the point where it cannot be tested on existing equipment. Another motivation for developing new tester technology is to reduce the cost of testing circuits that are produced in extremely high volumes.

Over the last few years, a new group of test solutions has significantly reduced the cost of test for commodity telecommunications ICs. These include subscriber line interface circuit (SLIC) and COder-DECoder (CODEC) ICs used in extremely high volumes in standard voice telephone systems, sometimes referred to as plain old telephone service (POTS).

The Buzz About Telecom

While more glamorous technology often gets the limelight, the traditional telecom IC market has shown consistent growth for many years (Figure 1). Not only is this caused by the addition of phone, fax, and modem lines in the United States, but also by growth in developing nations. This market has great potential when you consider that over half the people in the world have never even made a telephone call.

The increase in digital-based phone services such as Integrated Services Digital Network (ISDN) and Personal Communications Service will only accelerate this trend. Instead of just requiring analog-to-digital coding on every phone line, these services need analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) on every single phone.

CODECs and SLICs, despite their workaday applications, actually are difficult to test. The analog performance of these ICs, including the ADCs and DACs, is very demanding. For example, a tester must provide a noise floor in excess of 100 dB to adequately test these parts. Otherwise, a noise increase of just a few decibels over spec will show up as a significant increase in audible noise on the phone line. AC waveform accuracy also is a big concern, with requirements in the range of 0.003 dB.

The Next Test Challenge

Over 10 years ago, mixed-signal ATE vendors pioneered the test techniques that now are taken for granted in the telecom test world. Having mastered these techniques, the next goal is to attack the most significant issue for these devices—cost.

With volumes constantly ramping up, IC manufacturers are looking for ways to increase capacity while reducing the cost of test. Most telecom devices are tested on previous-generation test platforms. While these testers are fairly inexpensive, the number of testers required and the floor space needed to support them makes simply replicating existing solutions very inefficient. These older systems also use complex applications hardware that can be costly to maintain.

Some argue that newer-generation testers are too expensive to buy. Capital cost, however, really is not a useful metric when determining the best test solution. All that really matters is the cost added to each IC by the testing process.

Costs here not only include the price of the equipment, but also the added overhead of floor space, maintenance, handlers and probers, and operators. The trick is to reduce overhead costs or to spread the costs over more ICs. The latter is accomplished by doing one thing—increasing throughput. Consider the following options:

• Using most cost models, cutting test time in half decreases the cost of test per IC far more than cutting the cost of the tester in half.

• A current-generation tester, on a single-site basis, cuts the test time of most telecom devices by a factor of at least two or three vs previous-generation testers.

• A newer tester can support simultaneous testing up to 16 SLIC or CODEC channels.

It is possible to improve the throughput of SLIC and CODEC testing by a factor of 10 to 30 times by implementing applications using a newer tester and multisite test techniques. With this type of throughput improvement, the capital cost is practically insignificant.

In some situations, buying a current-generation tester to increase capacity with multisite testing results in the same cost of test as getting additional previous-generation testers free. This is because of the increase in throughput and a decrease in overhead costs per IC tested. With the boom in commodity telecom devices, many manufacturers simply do not have the floor space at any price to contain the single-site testers required to keep up with demand.

Multisite Testing Requirements

ATE must have some very specific features to facilitate mixed-signal multisite testing. For example, every DC and digital signal processing (DSP) instrument should analyze its own measurements, apply limits, and return pass/fail information.

Ask the question: “Would you perform digital pattern testing by collecting the digital outputs of a DUT and later comparing them mathematically to expected results to figure out if the part passed?”. Of course, the answer is no.

So the next question is, “Why do that for analog data?”. With multisite testing producing up to 16 times as many DC and DSP measurements as single-site solutions, why save up all that data only to have to crunch it serially in the central test computer? As any digital test engineer will tell you, multisite testing only works well if:

You do not have to share instruments between sites.

Each instrument analyzes its own data.

Significant test-time improvement for mixed-signal applications can be achieved only if these two things are true. Figure 2 shows a tester architecture that realizes true independent testing of each site. In this tester, each instrument (digital pins, DC pins, and DSP pins) makes a true parallel measurement and analyzes its own data, returning a pass/fail flag to the system controller along with numerical results.

Switching a single DC meter or DSP digitizer around four sites is not the same as parallel testing. If this kind of serialization is used, quad-site testing has bought you nothing.

Additionally, writing a multisite test program is far more difficult if you cannot really do things in parallel. Ideally, a multisite program must look just like a single-site program with all sites mimicking the first. If the program has to sequentially make measurements using shared instruments or sequentially analyze data collected from different sites, then a multisite test program begins to look very messy indeed.

The tester also must have a multisite datalogger that automatically sorts measured results to the appropriate sites. The tester software should manage tester instruments by disabling pins for sites that have failed previous tests when fast binning is enabled. This allows you to write programs that convert easily from testing one site to testing multiple sites.

Can This Help Me?

Voice-band telecom ICs are only one area in which multisite testing can be applied to lower the cost of test. Other potential applications include multimedia ICs, such as those conforming to Intel’s AC97 standard, and high-speed communications ICs, such as ISDN or Asymmetrical Digital Subscriber Loop. All of these have similar test requirements that lend themselves to straightforward multisite testing.

If you have cost-sensitive ICs running on a low-cost tester with increasing capacity requirements, chances are that multisite testing on a newer-generation tester can lower test costs while providing increased capacity. In addition, a newer-generation tester has the capability to grow with new technology. Many IC manufacturers are developing new products for applications such as RF or high-speed data communications that require more sophisticated test capability than they currently own.

A truly modular tester provides a single platform that tests everything from telecom to datacom, RF, disk drive, or smart power. The result is a solution that not only tests the latest and greatest IC, but also makes economic sense.

About the Author

Ken Lanier is the market manager for telecom, datacom, and multimedia at LTX. Before joining the company, he held positions in test applications engineering, engineering management, and product management. Mr. Lanier received a B.S.E.E. from Worcester Polytechnic Institute in 1984.

LTX, Fusion Division, LTX Park at University Ave., Westwood, MA 02090-2306, (781) 329-7550.



Copyright 1998 Nelson Publishing Inc.

October 1998


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