Today’s deep submicron system-on-a-chip (SOC) CMOS semiconductor technology is creating a new generation of electronic products that spans a broad range of applications. The key benefit of SOC technology is its capability to integrate primary system functions on one piece of silicon.
Hewlett-Packard has coined the acronym MACH-D to describe the features of a test system needed to address these devices. The following are examples of these functions:
FPD Interfaces
A predominant signaling technology used for FPD interfaces is LVDS. Currently, devices are available that have transmission speeds of hundreds of megabits per second and voltage swings of 350 mV. In the future, these data rates will increase to 1.6 Gb/s, and the voltage levels will decrease to 250 mV. The high data rates, low power, and low EMI make it an ideal solution to transmit data between a graphics controller and an FPD—and a challenge to test.
Critical tests for LVDS devices are data skew, PLL jitter, and at-speed functional tests. Today’s reduced speed or static tests, including scan and IDDQ, do not reveal or detect 100% of the deep submicron CMOS fault types, such as delay faults. If high-speed buses are not characterized and tested at speed, device quality and interoperability are at risk.
PanelLink Description
PanelLink, an LVDS-based FPD interface, uses signal channel data transmission at speeds of hundreds of megabits per second on a PCB or balanced cable. The physical layer of PanelLink may be described as four parallel LVDS channels.
Current PanelLink devices use an input clock speed of up to 85 MHz with an 8b/10b encoding scheme that results in a serial data stream running at 850 Mb/s. This speed was adequate for laptop displays. But for larger FPDs that will be connected to desktop systems, SXGA and UXGA resolutions will push the clock speeds to 112 MHz and 162 MHz, with the resulting transmitter speeds to 1.12 Gb/s and 1.62 Gb/s.
Figure 1 is a block diagram of both a PanelLink transmitter and a receiver. The red, green, and blue signals, along with control lines and a clock, are inputs to the transmitter.
The PanelLink transmitter converts these 24 inputs, plus five control bits, display enable, and a clock, into three differential data signals at 10 times the input frequency and one differential clock signal. The output clock is used as a reference frequency, not to latch the data. TMDS™ is an acronym for transition minimized differential signaling.
AC Test: Data Skew
The data-skew specification requires that the PanelLink data-bit positions in a cycle be measured relative to each other. The timing and specification for functionality at 85 MHz are shown in Figure 2. A vector pattern toggles each bit at 850 Mb/s, and a global search test is executed to measure the rising/falling edge of the TMDS signal and the PLL clock. One global search is executed for each bit. All three outputs can be measured in parallel for each bit.
AC Test: PLL Jitter
The PLL clock output runs at the same frequency as the input clock signal. The transmitter tests are performed with the clock in a frequency range of 20 to 85 MHz. PLL clock jitter is measured with a cycle-to-cycle jitter of ±2 ns applied to the input clock signal while data inputs are switching. Jitter of 2 ns represents the worst-case displacement in the clock edge of most graphics controllers.
Two device cycles are defined in the timing setup to mimic a -2-ns and +2-ns change in the rising edge of the input clock. Multiple device cycles are used in the vector setup to induce the jitter by switching device cycles in the vector pattern. The specification for jitter at 85 MHz is 200 ps.
At-Speed Functional Test
The challenge for functional testing of PanelLink devices is to match the speed at which the serial data must be applied and measured. The actual placement of the strobes is determined through the use of equation- based timing. The value of offset is determined in a prior test block that measures the propagation delay from the input clock to the first output data edge. This offset is added to the fixed-bit position in the serial stream to determine the edge positions for each strobe.
Two tester cycles are used to generate the clock, data, and measurement strobes. Each of these tester cycles represents half of the 10 bits of data clocked through the device. The equations that generate this timing are as follows:
offset = (value derived by spec search and passed to this timing set)
Cycle = 1/CLKINfreq à @ 85 MHz = 11.76 ns
Tester Cycle = Cycle/2 à @ 85 MHz = 5.88 ns
Bit_time = Cycle/5
Half_Bit_time = Cycle/10
Bitpos0 = offset + Half_Bit_time
Bitpos1 = offset +3*Half_Bit_time
Bitpos2 = offset +5*Half_Bit_time
Bitpos3 = offset +7*Half_Bit_time
Bitpos4 = offset +9*Half_Bit_time
Because the offset changes with frequency, the strobe positions will vary to obtain a passing functional test. To overcome this, a spec search test function is executed before the functional tests to find the propagation delay or value of the variable offset. The value found for offset then is passed to the equations so the edge positions can be recalculated.
Memory Interfaces
As microprocessor speeds have exceeded 500 MHz, they have outstripped the bandwidth available in today’s memories. The latest Rambus memory interface is available with transmission speeds running 800 Mb/s per wire across a two-byte bus (16 or 18 data lines). The setup and hold times have been reduced to the 200-ps range. This yields a memory bandwidth of 1.6 GB per channel with multichannel capability on a single SOC device.
Figure 3 shows the three main parts of Rambus memories: the interface, the channel, and the DRAMs themselves. An ASIC macrocell called the RAC is part of the interface design and is used in SOCs to interface the core logic of a CMOS ASIC device to the high speed Rambus channel. The primary function of a RAC is to perform the parallel-to-serial conversion of wide SOC buses to and from the narrow bus that communicates to the external DRAM devices.
At-Speed Functional Test
On a memory interface, the clock typically runs at the same rate as the data, with address and data latched on a single edge, rising or falling. New packet protocol memories use source synchronous clocking, with data latched on both the rising and falling edges of the clock. On RAC, for example, the clock runs at 400 MHz with data and address running at 800 Mb/s.
Two other at-speed issues for testing RAC are bus turnaround time and reflections. A dual transmission line setup typically is required to ensure zero turnaround time on a bus (Figure 4). With this well-known technique, a device operates in a nearly perfect terminated transmission line environment. Using a dual transmission line usually requires two test-system channels to test each high-speed signal. On the receive side, the signal is terminated with an additional circuit to ensure minimal reflections.
Reflections in the Rambus environment can cause devices to malfunction. For example, spurious reflections from mismatched impedances will cause a test system to pick up data that is not there or misinterpret existing data. A clean environment with matched termination is important for reducing any reflections from either the test system or the device driving the transmission line.
Setup and Hold Time Test
Two critical tests on a high-speed memory interface are the setup and hold tests. Typically, a surround by complement (SBC)-formatted data input is applied relative to the clock edge, and the two parameters are tested simultaneously. This requires three timing edges per data cycle.
At high speeds, however, only delay not return to zero (DNRZ) formats can be used. Because of the edge rates and the numbers of edges available, test systems cannot apply an SBC at the required speeds. DNRZ formats require a two-pass test with setup time TS (Figure 5a) tested with the data input shifted in one direction, followed by hold time Th (Figure 5b) with the data input shifted in the other direction.
In addition, special attention must be paid to input data. Since the SBC format guarantees a failing data bit on either side of the valid data, the simulation data applied during the test also must guarantee it, otherwise the test cannot determine a pass/fail boundary condition for that given cycle. For example, a data stream of constant ones or zeros would not effectively test the input setup and hold time.
Conclusions
High-speed buses for FPDs or memory, such as PanelLink and RAC, present several of the many test challenges created by SOC technology. Regardless of the SOC functionality mix, the optimal ATE platform for SOCs needs to be flexible.
To make testing accurate, repeatable, and result in the highest, most consistent yields, the test system must meet the functional and specification requirements for performing all SOC MACH-D tests. For high-speed bus testing, this translates into ATE platforms with the following general hardware characteristics:
Data rates of ³ 1 Gb/s.
Edge-placement accuracy of £ 100 ps.
System architecture that provides a low noise floor and minimal induced jitter.
Test Processor Per Pin that supports local sequencing, an algorithmic pattern generator with unlimited XYZ width, and wide scan.
Synchronous analog instrumentation.
About the Authors
Greg Geary is a sales development engineer at Hewlett-Packard. During a career of more than 20 years in the field of ATE, he also has been a marketing manager at Automated Test Engineering. Mr. Geary studied for a B.S. in electrical engineering at MSOE. Hewlett-Packard, 5301 Stevens Creek Blvd., M/S 54L-32, Santa Clara, CA 95052-8059, (408) 553-7895, e-mail: [email protected].
Zoe Butler, an applications engineer at HP, has been with the company for five years, including two at the Semiconductor Test Division in Germany. Previously, she was a mixed-signal design engineer. Dr. Butler received a B.Sc. and a Ph.D. from Edinburgh University, Scotland.
Philip Callahan is a product marketing engineer at HP. In the semiconductor industry for 12 years, he has served as a product engineer, an applications engineer, and a mixed-signal design engineer for TI and NCR Micro, now known as LSI Logic. Mr. Callahan has a B.S.E.E.
Matthias Kamm is a technical consultant working with HP’s family of digital test systems. He received a B.A. from Oberlin College, a B.S.E.E. from the University of Pennsylvania, and an M.S. from Santa Clara University.
Copyright 1999 Nelson Publishing Inc.
June 1999
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- Memory—embedded flash, embedded DRAM, and embedded SRAM.
- Analog—discrete analog components such as analog-to-digital and digital-to-analog converters, amplifiers, comparators, and PLLs plus complete macroanalog functions such as RAMDACs, power supervisory circuits, CMOS image sensors, and audio, video, and mobile communications baseband circuitry.
- Communications Interfaces—embedded physical-layer interfaces for Ethernet, Fibre Channel, IEEE 1394 (FireWire™), ATM, cable modems, and telephone modems.
- High-Speed Buses—memory interfaces, such as those used by the Direct Rambus™ RAC (Rambus® ASIC Cell) or the PC133 interface standard; low-voltage differential signaling (LVDS)-based flat panel display (FPD) interfaces such as PanelLink™, FlatLink™, and FPDLink; and system buses such as a microprocessor bus and an accelerated graphics port.
- Digital—high-speed digital applications, such as DSP cores, embedded CPU cores, PC-on-a-chip cores, PCI cores, microcontrollers, and graphics accelerators.