EMC Design Practices: Take Two PCBs and Call Me in the Morning Part 3

If the EMC characteristics of your electronic system are giving you a migraine, it’s time the PCB has a checkup. After all, the active devices that create our EMC headaches are all located there.

It does not seem to be widely known, but good PCB design can solve a lot of these headaches without additional cost. It also can’t be overstated—good PCB EMC design is our most important design element.

Because power- and signal-distribution technology has advanced so significantly from the point-to-point schemes used in the wiring of vacuum tubes and early transistor- based circuits, the older design techniques do not work to solve today’s EMC problems. In the past, PCB technology focused on high-production automated circuit manufacturing and uniformity. Uniformity was especially important for the front-end RF circuits of radios and televisions. Even then, these RF signals were low level and narrowband, and except for the input signal and local oscillator circuits, these early PCBs were not operating at particularly high frequencies. Today, the increased currents, higher speed broadband signals, and smaller board dimensions make PCB design for EMC absolutely necessary to meet both regulatory and functional requirements.

In most high-speed cases, PCB dimensions are several times greater than the harmonic wavelengths of the signals propagated on the board, forcing us to design each trace as a transmission line. For example, the propagation wavelength of the 10^th harmonic of a 600-MHz CPU clock on a PCB with a dielectric constant of 5 is only 4.5″ —and many CPUs are running much faster.

Currents flow from a source to a load and then return back to the source forming small loop antennas that are quite effective at higher frequencies. The loop efficiency increases with increasing frequency and loop area. As illustrated in Figure 1, layout must be considered because it plays an important part in EMC design.

High-frequency devices should be segregated from low-frequency devices and positioned as close as possible to the backplane and connectors. Conversely, they should be positioned as far as possible from the backplane and connectors when high-frequency signals don’t leave the board. This reduces the effects of capacitive and inductive coupling and helps prevent low-frequency circuits from being contaminated by high-frequency circuits.

There are four principal circuit-loop categories: low-level analog circuit loops, high-level analog and digital circuit loops, analog power circuit loops, and digital power circuit loops. Because most of these loops are synchronously driven, and 80 to 90% may be active at one time, layout and bandwidth control are critical to achieve the desired 100 ±20 dB reduction in RF emissions and susceptibility (immunity).

Analog Circuits

Typically, low-level analog circuits appear as narrowband filters coupled to small signal amplifiers. High-level analog circuits typically are narrowband oscillators with approximately sinusoidal outputs. In both cases, the circuits are steady-state. As a result, except for the switched-mode power supply noise from associated power circuits, analog circuits normally are not responsible for problem emissions from PCBs. Because they have a continuous input/output transfer function, any RF noise that exceeds the barrier potential of the many PN junctions in the semiconductor material of the various analog devices is a candidate susceptibility signal. Susceptibility occurs either from baseband noise coupled directly to and within the circuit’s passband or from audio rectification where the modulation envelope of an RF carrier picked up by the circuit is recovered and then processed by the circuit.

Digital Circuits

The same susceptibility problems may occur with digital devices. But since analog devices are 100 to 1,000 times more sensitive than digital devices, we normally associate this problem with analog devices. Analog power circuit loops tend to be quiet because analog circuits are steady-state.

Digital circuits are very noisy. So are their power circuits. The digital circuit’s on and off behavior creates very fast trapezoidal signal waveforms. These waveforms are made up of the fundamental, which determines pulse width, and an infinite number of odd and even harmonics of varying phase relationships that determine rise time.

Fortunately, for both EMC and circuit operation, we do not need all of the harmonics. The first nine or so will do. The rest we can eliminate, or at least try to. To make matters worse, the power supply output current follows the signal response as well.

Even though we may think differently, the power supply output is not steady-state DC during operation and also must be designed as a high-frequency circuit. EMC design for high-frequency circuits for both emissions and susceptibility requires that the layout minimize the RF coupling loop areas. The highest frequency loops should be kept as small as possible.

Two-Layer PCBs

For power distribution on two-layer boards, loop areas are minimized by keeping the power rails together as close as possible and by placing decoupling capacitors close to the active components that need protection. Decoupling capacitors do a good job for lower frequency circuits that do not operate at more than about five times the self-resonant frequency (SRF) of the capacitors. One way to extend the frequency range of a decoupling capacitor is to parallel the larger capacitor with a small value capacitor having low lead inductance.

SRF is largely determined by lead inductance, so anything that reduces lead inductance (shorter and wider) will increase the SRF and lower the RF emissions from the circuit. The use of bus-power distribution results in approximately 15-dB improvement in both the emissions and susceptibility of the PCB. The bus accomplishes this by reducing the rail inductance and providing a high quality decoupling capacitance across the rails, reducing the distribution impedance while increasing the SRF.

This technique is embodied in the multilayer PCB and responsible for its success. In this case, the small value capacitance created by the configuration lies between the power planes, has values that range from 50 to 1,500 pF/in.² (depending on spacing and dielectric), and has virtually no lead inductance.

If you have been following our series of articles, you are probably well aware that to control both radiated emissions and susceptibility of the high frequency circuit loops, it is important to minimize, minimize, and minimize. First, and most important, is the processing speed. Since high processing speed also is synonymous with broad bandwidths, we must carefully control the bandwidths because radiated susceptibility increases directly with frequency and radiated emissions increase as a function of frequency squared.

Starting with the highest frequency circuits, loop areas should be minimized. This may not be easy, but keep in mind that the multilayer configuration reduces circuit loop areas by as much as 40 to 60 dB.

Circuit bandwidths should be reduced as much as possible using low-pass filters. The limiting factor on bandwidth reduction using low-pass filters is the added delay. With clock speeds under 30 MHz, this approach cures our headaches most of the time. When it doesn’t, we also may have to add shielding. Shielding can be thought of as simply a high-pass filter that is used to minimize the radiated field. The broadest frequency range of attenuation results from combining filtering and shielding.

Referring to Figure 1, the signals from high-frequency circuit loops may remain on the PCB or they may leave. When the signal loops remain on the PCB, the circuit should be spaced at least 2″. away from any I/O circuits, especially the connectors. This spacing reduces both the inductive and capacitive coupling into the I/O.

On the other hand, when high-frequency signal loops leave the PCB and go elsewhere via connectors, backplanes, or cables, these circuits should be placed close to the connectors or backplanes. If placed further away, longer traces are required to bring these high-speed signals to the connector. This increases their loop area without changing their associated connector or backplane coupling. Since these circuits are hard-wired to the connectors, we can’t have any better coupling than that. This is especially important for two-layer PCBs where there are no signal reference planes.

Multilayer PCBs

The extra-strength solution is the multilayer PCB. It’s not the cure-all for EMC headaches, but it goes a long way toward being a universal cure.

Multilayer PCBs have the greatest parts density because they reduce the number of signal returns and all but eliminate power conductors, enabling the designer to reduce the size of various circuits on the board as well as its overall size. This is especially important in reducing propagation delay, keeping loop areas small, and minimizing the size of PCB-mounted shields.

The integral ground plane also makes possible the use of RF devices such as low-impedance microstrip and stripline transmission lines, waveguides and imbedded coaxial lines, and inductors/capacitors. The impedance of these integral RF devices can be tuned to minimize normal and forward/backward crosstalk, and reduce reflections from terminations.

Compared to a two-layer PCB, a simple four-layer PCB using microstrip signal distribution will provide approximately 30-dB improvement in EMC performance. This is accomplished by lowering the power distribution impedance and reducing the signal-loop area.

The power plane impedance is given by:

120 p (h/W)

Zo = ——————

Ö e

where: h = separation between planes or trace and plane

W= width of trace or plane

e = dielectric constant

Note: this equation is exact for h/W > 15

From the equation, we can see that making the planes wide and close together will reduce the power supply impedance.

Since the signal return is via the power supply return, running the signal traces over the power supply return plane reduces the signal loop area by several orders of magnitude. It also rotates the plane of the loop so that it is normal to, rather than coplanar with, the PCB.

The microstrip impedance also is a function of the h/W ratio and can be modified easily by changing the trace width. Unfortunately, the loop still is on the exterior of the PCB, and although the loop area is substantially reduced, it still is subject to both emissions and susceptibility problems.

In essence, stripline is a shielded microstrip line formed by adding a ground plane over the microstrip. Clocks and other high-speed lines should be run as stripline. Stripline enables us to raise the EMC performance of the PCB to about 45 dB when compared to a two-layer configuration.

If the entire PCB were stripline, the components themselves would be the worst offenders. The principle component problem is lead inductance and this can be reduced by using surface mount devices. Surface mounted components in a stripline configured PCB will provide approximately 6 to 8 dB of additional attenuation.

The internal ground plane that makes microstrip and stripline configurations possible also provides inherent shielding and isolation of signal layers. Typical isolation between signal layers separated by a ground plane is in the order of 50 to 55 dB. This level of attenuation is very effective in reducing crosstalk between sensitive circuits.

Shielding

Ground planes also can act as image planes or as one side of a PCB-mounted shielded enclosure. PCB shielding is a noninvasive suppression technique that does an outstanding job of reducing both the radiated emissions and susceptibility of a circuit.

Since the shielding is not inserted into the circuit, it does not effect high-speed operation. In fact, it is the only suppression technique that does not effect signal integrity. Shielding could be used as a stand-alone solution to the EMC problem, but it would have to provide the entire 100 dB or so of attenuation. Not impossible, but certainly not nearly as efficient as first designing the PCB to provide 50 to 55 dB of attenuation and then adding 45 to 50 dB with shielding.

About the Author

Ron Brewer is vice president of EMC technical services at Instrument Specialties. He is a NARTE-certified EMC/ESD engineer with more than 25 years in EMC/ESD/Tempest engineering. Mr. Brewer serves on three technical committees and, as an internationally recognized EMC authority, has made more than 185 technical presentations in North America, Europe, Asia, and the Pacific. He also has been named a Distinguished Lecturer by the IEEE EMC Society. Instrument Specialties, P.O. Box 650, Delaware Water Gap, PA 18327, (570) 424-8510.

September 1999