Combining X-Ray and ICT Strategies Lowers Costs

Faster time to market, much easier test management, higher test throughput, and test cost savings are the tangible, highly visible results of testing our newest generation of line cards at Alcatel-Canada. The results are particularly encouraging because we use a combination of X-ray inspection and simplified, reduced-probe in-circuit test (ICT) instead of the multiple–or split—ICT fixtures used with the previous generation of line cards.

We compared these test strategies using two very similar, complex cards (Table 1). They were evaluated with the same design-for-manufacturing analysis, built using similar components, designed with similar circuitry, and assembled with the same manufacturing process. These two cards provided the ideal case study for conducting an accurate comparison of two different test strategies.

Card Complexity Changes

Alcatel builds next-generation networks, delivering integrated end-to-end voice and data solutions to established and new carriers worldwide. Over the past few years, the complexity of the cards for these products has increased dramatically. Although physical card size has not changed much, designs have more densely packed an increasing number of electrical nodes and components into the area. This leaves less room for test access.

While the average number of nodes on these large cards continues to increase, the number of accessible nodes actually decreases. Tighter card design density, with larger device packages and more numerous bypass capacitors, affords less room for test pads. Card operation speeds also preclude test access to some nodes. These changes in card complexity have influenced our overall test strategy.

Test-Strategy Evolution

For several years, the 3070 ICT System from Agilent Technologies has been a cornerstone of our test process, providing full electrical test to verify the manufacturing process. This strategy was successful, but by 1999, we had begun to supplement ICT with X-ray inspection. The Agilent 5DX Automated X-Ray Inspection (AXI) System was our tool of choice, helping us locate and identify solder defects and missing components prior to ICT.

We were producing some cards with as little as 50% electrical test access. We also began building cards that exceeded the effective node count of our ICT systems. With these trends continuing, we saw a need to investigate methods that could increase the effective node count of our ICT equipment or reduce the probe access requirements on these and future cards.

The test system’s effective node capacity is equal to the maximum in-circuit resources reduced by the average number of blocked and double-wired resources. For example, although we upgraded to a 5,184-node count system, the effective tester capacity was only 4,400 nodes. The average blocked testhead resources and the double-wired card nodes reduced the usable tester resources by 15% to 20%. We could reclaim some of these resources by using wireless fixtures; however, our card’s maximum node size still remained significantly higher than the effective tester capacity.

To increase the testable in-circuit nodes, we used a multiple-fixture approach to ICT. This strategy, commonly known as a split-fixture approach, tests approximately half the card with one fixture and the other half of the card with another fixture.

Each fixture actually tests more than half of the card, redundantly probing several nodes. This ensures that each device is fully probed and each fixture probes power, boundary scan test access ports, and disable nodes. The cards are tested and repaired at each stage to ensure that all shorts have been removed prior to powering up the card.

To minimize the need for electrical test access, we initially used three techniques:

• Boundary scan interconnect test analysis.
• Alcatel custom resistor/digital cluster analysis (Figure 1).
• Alcatel custom analog cluster analysis.

We manually implemented these probe removal techniques on the initial card in this study. Since that development, we have produced custom scripts to identify potential probe removal for the resistor/digital cluster and analog cluster analyses. We also used the Agilent Access Consultant tool to remove boundary scan interconnect probes.

By the year 2000, with further increases in card densities, we observed process problems with the split-fixture test approach, including longer test cycle times, complexity of fixture handling, and increased fixture cost. We required more aggressive and targeted probe removal. Because of this, we supplemented our earlier probe-removal strategies with Agilent’s AwareTest xi software.

A New Approach

AwareTest, described in Figure 2, combines the capabilities of the in-circuit tester and the AXI system in a single test step, providing better coverage than either approach alone. AwareTest takes advantage of the defects detected by the AXI system and intelligently removes the need for in-circuit probe access without compromising our ability to verify proper component placement.

For example, when testing a digital device (U2 in Figure 2), AXI verifies that the device has been properly placed and that the device pins do not have any shorts or opens. The in-circuit tester then only needs to test a single device element to verify that it is operational, has been loaded with the correct part, and has not been loaded upside down.

Consequently, the software removes probe access from the device’s other elements. Similar techniques intelligently target probe removal from other devices. This technique now is being used to test our most complex cards where physical access is an issue.

Test-Strategy Comparison

One of our first large-quantity cards tested by AwareTest was the 16MRL, a 16-channel Multi-Rate Line card. As we brought this card into volume manufacturing, we decided to compare its test results with those of the previous-generation 8MRL, an eight-channel Multi-Rate Line card. The 8MRL was tested using a multiple-fixture ICT System.

The AwareTest software analysis was executed on the 16MRL prior to card layout. This enabled our CAD layout department to provide test access only to the electrical nodes identified by the software, rather than spending weeks to maximize electrical access.

We also used a slightly different approach in the X-ray inspection of these two cards. We tuned the AXI to minimize escapes on the 16MRL card but did not specifically do that for the 8MRL. Figure 3 compares the ICT results of these two cards.

Higher First-Pass Yields at ICT

We achieved a 59.8% first-pass test yield on the 16MRL card and only 26.7% on the split-fixture application. Several factors contributed to this result:

• The smaller, more reliable fixture produced a more stable and efficient test fixture/program.
• There was a reduction of fixture maintenance repair actions, 1.78% vs. 6.78%.
• There was a much lower occurrence of solder shorts and opens faults, 5.4% vs. 21.4%. The majority of this improvement was due to tuning the upstream AXI process to minimize escapes.
• ICT repair operators more quickly diagnosed true card failures and eliminated many card re-tests.

Higher Overall Test Throughput

On average, the 16MRL traversed the ICT repair loop only 0.75 times, compared to the 8MRL’s 4.52 times.

Better Test Management

Initially, the eight-channel line card’s ICT required three stages: shorts and unpowered testing with fixture A, testing with fixture B, and powered testing with fixture A. Using AXI prior to ICT ensured that the tested cards contained no shorts, so the multiple-fixture ICT process could be reduced to two stages: all tests with fixture A, then all tests with fixture B.

Even this simplified process caused a management nightmare, especially in the repair loop. Repair operators had to concentrate carefully to ensure that the repaired cards returned to the appropriate step of the multiple fixture test process. This, combined with the fixture-related failures, produced very inefficient and unsatisfactory overall results.

On the 16-channel line card, we perform only one ICT with a reduced set of probes. With only one fixture, the ICT management problems vanished.

Faster Time to Market

Incorporating probe removal into the card layout greatly simplified the CAD layout process, cutting the time to place test pads by more than half. This also helped start the test-development process earlier, resulting in quicker availability of the in-circuit tester. In addition, we tested the prototype cards using only the AXI, rather than waiting for the in-circuit fixture and program. This has resulted in faster turnaround at the prototype design stage.

Lower Test Cost

This newer process also provided a great economic advantage. Single-fixture cost is much less than half the cost of using multiple fixtures at ICT because of fewer nodes. Only 2,728 nodes are required, whereas each of the split fixtures had more than 3,100. Reduced fixture repair and higher ICT reliability also provide more efficient use of operator and system test time.

Conclusion

The 16MRL card turned on extremely well, producing a 93% initial volume production functional test yield, higher than the 90% yield of the eight-channel line card after a full year of production test modifications.

Our functional test goal was to maintain the existing yield and not impact it by changes to the upstream process. We clearly exceeded this goal with the AwareTest results on the 16MRL card.

About the Authors

Miro Kierkus, the manager of structural test engineering at Alcatel-Canada, has 12 years of design and test experience. He has a bachelor’s degree in electrical engineering from the University of Western Ontario and a master’s degree in electronics from Warsaw University of Technology. e-mail: [email protected]

Roy Suttie is the test engineer at Alcatel-Canada and has 14 years of experience in the industry. Mr. Suttie received an electronic engineering technologist diploma from Conestoga College of Applied Arts and Technology. e-mail: [email protected]

Alcatel-Canada, 349 Terry Fox Dr., Kanata, ONT K2K 2E7 Canada, 613-591-3600

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September 2002