Optimizing COT for SOCs requires a new way of thinking.
Cost of test (COT) is of paramount importance to semiconductor manufacturers. COT financial models are widely used for determining the COT for ICs and ATE selection. Over time, ATE manufacturers have developed equipment taking these criteria into account.
These modeling tools, however, were developed and refined in an era when semiconductor chips were manufactured in very high volumes and had reasonably long life cycles. Many device types such as microprocessors and DRAMs continue to fit this assumption, but system-on-a-chip (SOC) devices typically do not. Using these COT models as criteria in ATE acquisition, without taking into account the fact that SOC realities are different, actually has increased the overall COT for SOC suppliers.
The rapid introduction of successive generations of SOCs, each exhibiting higher levels of performance and integrating more analog and digital functions, has created a new range of innovative and affordable consumer products. In the process, DVD players have plummeted in price from several hundreds of dollars at introduction to less than $50 in just a few years. Satellite receivers now are free in exchange for a subscription contract.
Unfortunately for SOC manufacturers, this gives the SOC business some characteristics that are—in the aggregate—unique to this segment of the semiconductor industry. Some of these characteristics include the following:
- Rapid product innovation via increasing integration of complex intellectual property (in-house and external, analog and digital).
- Unpredictable market demands.
- Shrinking product life cycles.
- Unrelenting cost pressures.
SOC manufacturers are caught in a technology spiral that requires continuous innovation to remain competitive. This drives them to design very complex devices on leading-edge processes that continue providing the system manufacturer with compelling cost/performance and features.
At the same time, SOC manufacturers face a high degree of market unpredictability. It is impossible for them to accurately predict which SOCs will be market winners and which will be dogs. Competitors may come to market earlier with a similar product and get the design win, or the market may not develop as quickly as hoped. In either case, the volumes may never materialize.
While some semiconductor devices have significant volumes over a number of years, SOCs have volume life cycles typically measured in months to obsolescence. Today’s state-of-the-art SOC device is quickly replaced by a new one exhibiting higher performance and more functionality.
Making matters worse, the average selling price of the devices undergoes severe erosion shortly after introduction. The market rewards the early entrants before competitors drive down prices in competition for a limited number of device sockets.
Key COT Modeling Parameters
Comprehensive COT modeling of an ATE test cell requires a fairly large number of parameters and can be a demanding task. The key parameters are acquisition or capital cost, test time, space, utilization, yield, and spares and maintenance costs.
The remaining parameters tend to have similar values independent of the ATE choice. As such, they form part of the overall COT but usually are not deciding factors in ATE selection: operator-manning rates, tooling costs, indirect materials and consumables, retest rates, prober/handler cycle time, and lot sizes.
Here’s a short review of the key factors, together with a look at how they should be modified to produce lower overall COT in an SOC world.
Acquisition cost is the purchase price of the equipment plus any facility improvements required to make it operational. Facility improvements may include a provision for chilled water, if none was previously available, as well as the reinforcement of flooring or increased ceiling height required by some SOC ATE.
This cost is amortized in the COT model over a period of years, typically three or five depending on the company and financial reporting rules. The ICs going out the door are burdened with a pro-rata share of this cost, and obviously, the smaller this cost the better.
Acquisition costs and the resultant depreciation budget tend to be the dominant constituents of COT. Indeed, broad-spectrum independent device manufacturers find that they can profitably market some low-cost devices simply by testing them on fully depreciated testers. Using these free testers gives them the lowest possible COT and allows them to generate reasonable margins on those devices.
|Depreciation Period:||Three Years|
|300-mm Wafer Prober Cost:||$300k|
|Manning Rates:||Operator—25%, Technician—25%, Engineer—25% per Tester|
|Annual Labor Rates:||Operator—$60,000, Technician—$70,000, Engineer—$90,000|
|Available Time:||98% Uptime|
|Spares/Maintenance Costs:||10% of Total ATE + Prober Acquisition Price|
|Facility Costs:||$20,000 ($100/yr/sq ft for 10 ft × 20 ft Test Cell)|
Figure 1. COT of a $1M Test System
To illustrate the impact of acquisition costs, Figure 1 shows the hourly COT for an SOC test cell consisting of a test system with a $1 million acquisition cost and $300k for a 300-mm wafer prober. Because yields vary between companies, we’ve simplified the analysis by assuming the yield is 100% and normalizing the data to an hourly operating cost.
With SOCs, the equipment easily can be rendered obsolete long before the amortization period. The short device life cycles, increasing levels of performance, and on-chip analog content can quickly result in test requirements beyond the capability of the equipment.
Some SOC manufacturers hedge this possibility by buying more capability than they need. This increases the acquisition cost and the COT by 20% or more and exacerbates the COT problem if the device doesn’t reach high manufacturing volumes. Given the unpredictability of the markets, it also is difficult to ensure that the extra capability actually is what will be needed later. The impact of over-configuring a tester by 20% raises COT by approximately 12%.
Test time is made up of several factors. In a simple analysis, the average test time for a good device and the average test time for a bad device are all that is needed, together with the yield, to compute the throughput. Handler cycle time must be considered as well.
Parallel test often is used to lower the overall COT. This is based on the premise that multiple devices can be tested—in parallel—in less time than if done serially. Memory devices are a prime example. With parallel tests, the device throughput model gets a little more complicated since the average throughput now is affected by the probabilities of good and bad devices at each site.
Buying new ATE for SOC test applications in configurations specifically for parallel test is not common. Instead, the configuration, such as pin-count, primarily is determined by the most demanding device test requirement. Parallel test then is opportunistically performed on smaller devices that still are in manufacturing. SOC manufacturers often don’t know a-priori which devices will go into high volume and benefit from parallel test.
Floor space is important, especially if the ATE will be placed in a clean-room area. Depending on whether it is a class 100 or a class 1 facility, burdened floor space can range from $50 to $500 or more per square foot per year.
Utilization is the percentage of time the equipment actually is used for production testing and excludes time for engineering use, calibration, and repair. Obviously, the higher the utilization, the lower the COT. If the equipment is not testing in production, it is not being used for COT purposes even if there are no parts to be tested. Even world-class manufacturers of high-volume devices have difficulty reaching equipment utilizations of greater than 90%.
Sadly, it is not unusual to see ATE sitting idle on an SOC test floor while devices are waiting in work-in-process queues simply because there are not enough testers with the right configurations available. This results from unanticipated market demands and even happens in cases where the equipment was over-configured at acquisition time.
Device yield has a significant lever over COT. Unfortunately, when a COT model is used to evaluate a purchase decision, it is difficult to translate between the equipment’s accuracy specifications and the resultant effect on yield unless actual data can be obtained by experimentation.1 Often you can get a reasonable estimate based on results from prior-generation devices.
Manufacturers of devices sold under different speed grades are keenly aware of the profit differences accrued by their capability to up-bin devices. For that reason, they use more accurate test systems and adjust their comparative COT models accordingly.
Unfortunately, many COT models compute the economic effects of ATE yield losses as scrap costs. It would be more accurate to look at it as lost revenue, especially when dealing with SOC devices that usually are in the early stages of the yield curve due to their short life cycles.
Many fabless SOC manufacturers are steered by test houses to use installed test capacity under the guise of lower test-system rental costs. Frequently, the systems in question are not up to the needed accuracy or performance. This can result in increases of Type I or Type II yield errors.
A Type I error is the probability of rejecting a good device due to the extra guardbanding needed by the tester. A Type II error is the probability of passing a bad device if the guardbands are insufficient. These errors can be costly in the long run.
Type I errors will result in building more wafers to achieve a specific volume and requiring more equipment rental hours to test the extra devices. Type II errors can have drastic consequences. An SOC manufacturer that ships unacceptable-quality devices risks having its devices designed out of a product.
Spares and Maintenance Costs
Spares and maintenance costs depend on the reliability of the test system or mean time between failures (MTBF) and the turnaround time for spares from the equipment manufacturer (spares replenishment time). All things being equal, a system with a high MTBF and a small number of board types needs fewer spares. Also, a system designed so most repairs can easily be addressed by in-house technicians will result in lower service contract costs and faster mean time to repair (MTTR), making more time available for production.
In the dynamic world of SOC test, new test platforms are brought in every device generation or so, and the investment in training and spares buildup is in a constant state of flux. This results in an escalating spares budget and specialization of in-house technicians around specific platforms, adding to the COT.
The DFT Factor
Another important factor to consider in COT is design for test (DFT). There is an industry-wide move to include more DFT and structural tests in devices to achieve faster time-to-volume (faster test-program generation), improve test quality, and realize lower COT.
Device characterization and design validation still require a full-capability test system. But as more DFT is implemented, lower-cost equipment can be used in manufacturing tests. This is illustrated in Figure 2.
Figure 2. Manufacturing Test Migration to Structural Test Reduces COT
The COT savings depend on the amount of DFT that can be used in the devices being manufactured. DFT is not free; there are costs involved besides the usually small amount of additional silicon real estate used. For the reader interested in exploring this aspect, there are several excellent sources available.2
A few SOC manufacturers have developed a level of DFT expertise that allows them to make and ship most devices with only structural test methods used in production. Others have developed sufficient expertise to seriously consider adopting a distributed test strategy to lower their COT. 3
Ideal SOC Test System For Lowest COT
Now that we’ve examined the major factors and how they affect the SOC COT, we can determine exactly the ATE features that will let us redefine the COT for SOC devices.
Low Acquisition Cost
As we saw in Figure 1, depreciation dominates the COT. As a result, the largest initial impact on the COT is made by an architecture that provides the needed capability at the lowest possible cost. Suppose that the tester in Figure 1 could be purchased at half the price. That would drive down the COT to $78 per hour from the original $114, a 32% reduction.
Since the lowest COT is achieved only when the test equipment has been fully depreciated, the ideal architecture not only is cost-effective at the time of acquisition, but also can be continuously evolved in the field after its deployment. In this manner, the acquisition cost is fully amortized, and the tester is free for subsequent generations of SOC devices.
The system can be deployed initially with the exact configuration needed for the current SOC device test. Later it can be upgraded with the features needed, be it more pins, higher or lower performance, additional mixed-signal instrumentation, or more powerful device power supplies.
Likewise, there is no need to over-configure the system as device volumes increase and extra capacity is needed. We call this 4D-scalability. Figure 3 illustrates this point. In this case, we start with a fully depreciated test system, install $100,000 of upgrades needed to test a new-generation SOC device, and mate it to a new 300-mm wafer prober. In fairness, we add the wafer prober since a fully depreciated system most likely would need a new prober. The 47% of cost in depreciation is mostly for the wafer prober.
Figure 3. Effect on COT by Upgrading a Depreciated Tester
Built-In Parallel Test
Parallel test will further drive down the COT of SOC devices. Parallel test support should be built into the test-system hardware and software with features like site-mapping hardware and multithreaded software to support concurrent, nontrivial test flows across multiple sites.
Parallel test also allows the tester’s instrumentation to be configured so resources can be made available on a per-site basis if COT analysis indicates this choice is optimal. This dual-mode flexibility further underscores the need for an architecture that truly does not have dedicated analog or digital slots.
The test system, even though it has a new set of capabilities, still must maintain a small test cell size.
Field Reconfigurable for Maximum Utilization
To quickly adapt the installed tester fleet as the SOC device mix changes the test requirements, the system must be field reconfigurable by the user in literally no more than a couple of hours. In other words, system reconfiguration should be accomplished simply by changing or adding PCBs and running some calibration and verification software.
The achievable accuracy must scale to maintain optimum cost/performance. Only high-performance channels require exquisite accuracy while lower cost/performance channels can have lesser accuracy. The system should support a performance mix of instrumentation without impairing attainable accuracy at one end or cost at the other.
Low Maintenance Costs
The system design should allow all preventive maintenance and repairs to be made by the user’s in-house technicians. Since the system we’ve outlined has an exceedingly long productive life, in-house technician training is extremely effective by eliminating the need for a typical service contract, and the spares inventory does not risk obsolescence.
We’ve identified the shortcomings of existing COT models when applied to the realities of SOC test. Modifications to these models are required to make an optimum financial decision over multiple generations of devices.
- Dalal, W., “The Value of Tester Accuracy,” International Test Conference, 1999.
- Dislis, C., et al, “Test Economics and Design for Testability,” Ellis Horwood Ltd.
- Garcia, R., “How to Succeed With Structural Test,” Evaluation Engineering, November 2001.
About the Author
Rudy Garcia is the strategic marketing manager and technical advisor at NPTest. He has more than 25 years of experience in IC test and is an IEEE member active in test-related forums such as the International Test Conference and the International Technology Roadmap for Semiconductors. Mr. Garcia also was the chairman of the Virtual Socket Interface Alliance Test Development Group in 1998-99. NPTest, a Schlumberger company, 150 Baytech Dr., San Jose, CA 95134-2302, 408-586-6531, e-mail: [email protected]
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