New to this year’s schedule are several tutorials for individuals interested in earning the association’s new ESD control program manager certification. Requirements for certification include attending specific tutorials and passing a final exam. The tutorials that are part of the manager’s certification program carry the PrM designation in the schedule that accompanies this article.
Tutorials, Papers, and Workshops
Three days of tutorials on Sunday, Monday, and Thursday (Sept. 21, 22, and 25) mark the beginning of symposium week. A range of classes from basic to advanced levels will be offered, many tailored to prepare participants for the NARTE certification exams given on Friday after the symposium. Tutorials in the following schedule with a T or an E following their titles have been selected as being helpful to a technician or an engineer interested in preparing for the NARTE exams.
Eight paper sessions run in two parallel tracks and an invited plenary session paper begin Tuesday (Sept. 23) and run through Thursday morning. The presentations, by authors from North America, Europe, and Asia, will represent areas such as RF ESD, testing and characterization, MR heads, modeling, discharge phenomena, and on-chip protection.
Eight interactive workshops will be held on Wednesday (Sept. 23). The topics range from ESD audits and clean rooms to trends in device and circuit simulation for ESD production development.
A stand-alone seminar on designing and implementing an ESD control program based on ANSI/ESD S20.20 also is part of the schedule. This program will explore the tools and techniques needed to help you prepare for an ESD facility audit. Registration is $1,495 and limited to 30 registrants.
Exhibits
Registration And Fees
The fee to attend the symposium is $495 for members and $595 for nonmembers on or before Aug. 8; after that, the cost is $695. Each full day of tutorials is $475 for early registration and $550 after Aug. 8; a half-day registration, either Thursday morning or afternoon, costs $275. The total package for ESD Association members is $1,725, $1,815 for nonmembers, and $2,110 for everyone after Aug. 8.
For additional information or to register for the EOS/ESD Symposium, visit www.esda.org. For hotel reservations, call the Riviera Hotel & Casino at 800-634-6753.
TUTORIALS
Sunday, Sept. 21
Tutorial A: ESD Basics; T/E
Technical Level: Basic/Intermediate
Tutorial B: ESD On-Chip Protection in Advanced Technologies
Technical Level: Intermediate/Advanced
Tutorial C: System Level ESD/EMI—Part 1: Principles, Design Troubleshooting, and Demonstrations
Technical Level: Intermediate
Tutorial C: System-Level ESD/EMI—Part 2: System-Level ESD Testing and Evaluation to the IEC ESD Standard
Technical Level: Intermediate
Monday, Sept. 22
Tutorial D: Air Ionization: Issues and Answers; T/E/PrM
Technical Level: Basic
Tutorial E: Packaging of Electronic Products for Shipment; PrM
Technical Level: Basic/Intermediate
Tutorial F: Application and Process Dependent ESD Design Strategy
Technical Level: Intermediate/Advanced
Tutorial G: EOS/ESD Failure Models and Mechanisms; E
Technical Level: Advanced
Tutorial H: How To’s of In-Plant ESD Survey and Evaluation Measurements; T/E/PrM
Technical Level: Basic
Tutorial I: ESD Control in Cleanrooms
Technical Level: Basic
Tutorial J: ESD Handling and Tool Design Practices for Extremely ESD-Sensitive Devices
Technical Level: Intermediate
Tutorial K: Circuit Modeling and Simulation for On-Chip Protection
Technical Level: Intermediate/Advanced
Tutorial L: Device Testing—Component-Level: HBM, CDM, MM, and TLP; E
Technical Level: Basic/Intermediate
Tutorial M: On-Chip Electrostatic Discharge (ESD) Protection in RF Technologies
Technical Level: Intermediate/Advanced
Thursday, Sept. 25
Tutorial N: ESD Standards and Procedures; T/E
Technical Level: Intermediate/Advanced
Tutorial O: Troubleshooting On-Chip ESD Failures
Technical Level: Intermediate/Advanced
Tutorial P: Electrostatic Calculations for the ESD Engineer; E/PrM
Technical Level: Intermediate/Advanced
Tutorial Q: Design of TLP-Systems and Applications of the Very-Fast TLP
Technical Level: Intermediate
Tutorial R: Organizing and Managing an ESD Program
Technical Level: Basic
Tutorial S: Transmission Line Pulse Measurements: Parametric
Analyzer for ESD On-Chip Protection
Technical Level: Intermediate
TECHNICAL SESSIONS
Tuesday, 10:30 to 11:45 a.m.
Session 1A: Advanced Power Clamps for On-Chip Protection
Moderator: Robert Gauthier, IBM Microelectronics
1A.1 A MOSFET Power Supply Clamp With Feedback Enhanced Triggering for ESD Protection in Advanced CMOS Technologies
1A.2 Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies
1A.3 Methods for Designing Low-leakage Power Supply Clamps
Session 1B: Trends in ESD Testing
Moderator: Horst Gieser, Fraunhofer-IZM
1B.1 Real World Charged Board Model (CBM) Failures
1B.2 A Wafer Level HBM Tester Delivering Pulses Through Transmission Lines
1B.3 Transmission Line Pulsed Photo Emission Microscopy as an ESD Troubleshooting Method
Tuesday, 1:30 to 5:30 p.m.
Session 2A: On-Chip Protection Strategies, Physics, and Modeling
Moderator: Gianluca Boselli, Texas Instruments
2A.1 ESD Protection Design Challenges for a High Pin-Count Alpha Microprocessor in a 0.13µm CMOS SOI Technology
2A.2 TLP Analysis of 0.125 µm CMOS ESD Input Protection Circuit
2A.3 Transient Latch-Up: Experimental Analysis and Device Simulation
2A.4 Characterization and Modeling of Transient Device Behavior Under CDM ESD Stress
2A.5 Thermal “Current Filament” Movement in an ESD-Robust DENMOS Transistor
2A.6 ESD Phenomena in Interconnect Structures
2A.7 Impact of Layer Thickness Variations of SOI Wafer on ESD Robustness
2A.8 High Abstraction Level Permutational ESD Concept Analysis
Session 2B: Discharge Phenomena in Theory and Practice
Moderator: Douglas Smith, D. C. Smith Consultants
2B.1 On the Development of Passive/Active Guard Electrode Systems for Human Body Electrostatic Discharge (ESD) Control
2B.2 Advanced Technology for Monitoring Plasma Lightning ESD Damage Using High-Frequency Magnetic Wave Sensors
2B.3 ESD Sensitivity of Devices on a Charged Printed Wiring Board
2B.4 New Methods for the Assessment of ESD Threats to Electronic Components
2B.5 A Physical Model to Explain Electrostatic Charging in an Automotive Environment; Correlation With Experimental Approach
2B.6 Characteristics of Unipolar Impulsive Fields From a Nearby ESD Source
2B.7 4.5-GHz Measurement of Transition Duration and Frequency Spectra Due to Small Gap Discharge as Low-Voltage ESD
2B.8 TLP Can Simulate dV/dt Found in Real HBM and MM Events
Wednesday, 8:00 a.m. to noon
Session 3A: RFIC and Novel Protection Devices
Moderators: Eugene Worley, Conexant Systems, and Robert Gauthier, IBM Microelectronics
3A.1 Comprehensive ESD Protection for RF Inputs
3A.2 Co-Design Methodology to Provide High ESD Protection Levels in the Advanced RF Designs
3A.3 ESD Protection Design for GHz RF CMOS LNA With Novel Impedance-Isolation Technique
3A.4 The Effect of Deep Trench Isolation and Sub-Collector Doping on the Electrostatic Discharge (ESD) Robustness of Radio Frequency (RF) ESD Diode Structures in BiCMOS Silicon Germanium Technology
3A.5 Study of Vertical SiGe Thyristor Design and Optimization
3A.6 STMSCR: A New Multi-Finger SCR-Based Protection Structure Against ESD
3A.7 Impact of Elevated Source Drain Architecture on ESD Protection Devices for a 90-nm CMOS Technology Node
3A.8 Area Compact, ESD Robust, Fully Silicided NMOS Using Novel Active Area Ballasting (AAB) Technique
Session 3B: Factory and Materials
Moderator: Thomas Albano, Eastman Kodak
3B.1 Creating and Measuring Photomask Damage
3B.2 Ion Imbalances on the Ionizer-Controlled Work Surface
3B.3 Use of Electrostatic Discharge Test as a Method for Full Characterization of Dissipative Conductive Materials
3B.4 Flue Gas Cleaning Using Wet Type Electrostatic Precipitator
3B.5 Biased Plate Characterization of Pulsed DC Ionizers
3B.6 Exploring a Clean ESD Protective Packaging Film and Its Ionic Contamination Methodology
3B.7 Test Procedures for Predicting Surface Voltages on Inhabited
Garments
3B.8 All-Polymeric Compounds: Conductive and Dissipative Polymers in ESD Control Materials
Thursday, 8:00 a.m. to noon
Session 4A: Characterization of On-Chip Protection
Moderators: Natarajan Mahadeva Iyer, IMEC, and Horst Gieser, Fraunhofer-IZM
4A.1 Coupled Bipolar Transistors as Very Robust ESD Protection Devices for Automotive Applications
4A.2 Test Circuits for Fast and Reliable Assessment of CDM Robustness of I/O Stages
4A.3 A Traceable Method for the Arc-Free Characterization and Modeling of CDM Testers and Pulse Metrology Chains
4A.4 Capacitively Coupled Transmission Line Pulsing CC-TLP: A Traceable and Reproducible Stress Method in the CDM-Domain
4A.5 Combined TLP/RF Testing System for Detection of ESD Failures in RF Circuits
4A.6 A Combined 50 and 500-Ohm Impedance TLP System
4A.7 Transmission Line Pulsed Waveform Shaping With Microwave Filters
4A.8 Standardization of the Transmission Line Pulse (TLP) Testing Methodology for Electrostatic Discharge (ESD) (In memory of Hugh Hyatt)
Session 4B: Magnetic Recording Heads
Moderators: Jeff Salisbury and Bert Perry, Seagate Technology
4B.1 ESD Phenomena in GMR Heads in the Manufacturing Process for HDD and GMR Heads
4B.2 A Consideration About Ionizer Balance in HGA Process
4B.3 Continuous Voltage Monitoring Techniques for Improved ESD Auditing
4B.4 Study on Magnetic Instability of GMR Heads Using Quasi-Static Tester With Laser Heating Function
4B.5 ESD SPICE Model and Measurements for a Hard Disk Drive
4B.6 Wrist Strap Monitor Testing for Use With the Latest MR Head Technologies
4B.7 Effects of ESD Transients on Noise in GMR and TMR Recording Heads
4B.8 Discharge Current and Electric Field Radiated From Small Capacitance Device
WORKSHOPS
Wednesday, Sept. 24
Workshops Chair: Larry Ting, Texas Instruments
Vice Chair: Thomas Albano, Eastman Kodak
Workshop Session A
1:30 to 3:00 p.m.
(Parallel Sessions)
A1. Common Auditing Issues
A2. How Does TLP Enhance ESD Design?
A3. On-Chip Protection for RF Technologies
A4. ESD in Cleanrooms
Workshop Session B
4:00 to 5:30 p.m.
(Parallel Sessions)
B1. ESD in Magnetic Recording
B2. Trends in Device and Circuit Simulation for ESD Protection Development
B3. ESD in Nanoscale Devices
B4. ANSI/ESD S20.20 Control Program Audit
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