On any given day, a certain percentage of the plastic-encapsulated components passing through an assembly line is defective in some way. The defect is less likely to be a chip-level electrical flaw that would already have been caught by testing and more likely to be an internal structural packaging flaw, which can be much harder to detect.
The task is to ensure that assembled product meets the OEM’s requirements for performance and longevity. This does not mean that all components and all products must be perfect. But it does mean that they must have sufficient electrical and structural integrity to last through what is considered a normal lifetime for the product.
To achieve this, reliability engineers can use information from at least five sources:
• The anticipated lifetime of the system into which a component is being installed. It might vary from a few years for a low-cost consumer product to a high-end military or aerospace system that may be required to function for decades.
• The functioning of the system within its anticipated environment. A pacemaker, for example, will experience very little in the way of thermal shock while a component in an under-hood automotive system will be exposed to considerable thermal shock.
• The structure of the part. As an example, the design of a lead frame-based plastic package can significantly affect the package’s susceptibility to damage from moisture and contaminants. Acoustic micro-imaging can be useful in examining internal details nondestructively.
• The results of accelerated reliability tests.
• Defect criteria such as those in the recently revised IPC/JEDEC J-STD-020D. Section 6.2.1.1 of the standard, for example, does not permit delamination on the active side of the die in lead frame-based packages.
One challenge is the great disparity between the number of plastic-encapsulated components that fail electrically because of internal damage and those that pass electrical tests even though they have internal damage. Damage in this instance actually describes two different phenomena: anomalies that occurred during the fabrication of the plastic-encapsulated component, such as a delamination caused by contamination on the lead frame surface, and anomalies that occurred after component fabrication.
Many forms of internal damage change and grow rather slowly. As a result, electrical testing after reflow may find only a few failures even though thermal cycling and environmental exposure may later cause a large number of failures.
Acoustic micro-imaging greatly simplifies the task of separating significantly damaged components from those with relatively harmless internal damage. Small, scattered delaminations along the lead fingers may be harmless in many applications. But more numerous delaminations, especially if they extend nearly the whole length of the lead finger, are classic anomalies that probably will pass electrical tests today but will fail in service some time in the future.
Figure 1 is the acoustic image of a thin quad flat pack (TQFP) used in a modestly priced consumer product. From the center outward, the features visible in the acoustic image are the die, the die paddle, and the lead fingers.
The lead fingers are very short, as shown in Figure 1. The red areas are locations where the mold compound is delaminated from the top surface of the lead finger. Although they are only faintly visible, wires extend from the edges of the die to the inner end of the lead fingers where they are attached by wedge bonds.
The wedge bonds are vulnerable to electrical failure because they can be attacked by moisture and contaminants. Such damage is especially likely to occur if a delamination extends along the whole length of the lead finger rather than just part of the length. J-STD-020D specifies that delaminations extending more than two-thirds the length of a lead finger are unacceptable.
Based on the acoustic image, how long will it take under ordinary service conditions for moisture and contaminants to reach the wedge bond and corrode it to the point where it fails electrically? Accelerated reliability testing with exposure to moisture may give a reasonably dependable answer. The component manufacturer’s previous experience with this component also may be helpful because some lethal-looking internal anomalies turn out to be mostly harmless.
Accordingly, many TQFPs with this type of internal damage might be acceptable in a low-end consumer product. In more stringent applications, however, such a component would almost certainly be rejected.
Other J-STD-020D failure criteria are less forgiving. For example, a crack that runs from any lead finger to any other internal feature always is considered a failure and understandably so since the crack might run between adjacent lead fingers. A crack that intersects a bond wire, ball bond, or wedge bond also is a failure.
Figure 2 is the acoustic image of the die in a plastic ball grid array (PBGA) package. Specifically, the acoustic image was made precisely at the depth where the mold compound interfaces with the top surface of the die and the die pads to which wires are bonded.
The PBGA was intended for use in a medical system where a failure could pose some degree of risk to a patient. In this system, the PBGA would experience normal thermal cycling along with relatively stable external conditions of temperature and humidity. Exposure to shock and vibration is relatively minor.
The key features in the acoustic image are four small delaminations, one at each corner of the die. Delaminations on the die face in lead-frame based components generally are serious because they can expand during normal thermal cycling. The rate of expansion is difficult to predict, and the result of expansion often is the intersection of the delamination with a bonded wire. The growing gap between the die face and the mold compound tends to sever the wire bond, causing electrical failure.
A small die face delamination proven to be relatively stable might be acceptable although such a delamination would probably be found on a device much less complex than a PBGA. The four corner delaminations shown in Figure 2 not only branded this component as a reject, but they also initiated an investigation of process controls to prevent similar anomalies from occurring in the future.
Figure 3 is the acoustic image of the interface between the die surface and the underfill layer which includes the solder bumps in an advanced flip-chip device for an automotive application. In its real-world application where significant longevity is required, the chief threats are from shock, vibration, and thermal excursions. This flip chip, however, was imaged acoustically because it failed reliability testing. Because of the small dimensions of the solder bumps, the very high acoustic frequency of 400 MHz was used to provide optimal image resolution.
This flip chip has two types of defects probably not related to each other. The irregular light areas are voids or air bubbles trapped in the fluid underfill material as it flowed across the standoff between the die and the substrate. Voids are more serious if they come in contact with solder bumps, and in this device, some of the voids clearly surround solder bumps.
Because a void contains air rather than epoxy, the solder bump can gradually extrude itself into an adjacent void. When enough solder has migrated in this way, the bump itself may crack, causing an open. Voids also are thermal insulators and, to some extent, prevent heat from the die to dissipate through the substrate.
The second type of defect in this flip chip is a crack or absence of bonding in some of the solder bumps. Red arrows identify three of the affected bumps in Figure 3.
In the acoustic image of solder bumps in a flip chip using this color map, you would expect to see the bump itself appear gray. However, these bumps appear black, indicating a high level of ultrasonic reflection caused by a crack or other gap. They may have internal cracks or simply may not be in contact with the bond pads on the face of the die.
Whatever the source, the failed bumps were the cause of electrical failure discovered during reliability testing. The gaps in these bumps do not seem to be related to the nearby voids. This flip chip appears to have two conditions—underfill voids and defective solder bumps—both of which must be corrected before the desired level of reliability can be achieved.
About the Author
Tom Adams is a freelance writer and photographer who has authored more than 500 articles for semiconductor and microelectronics trade magazines. Sonoscan, 2149 E. Pratt Blvd., Elk Grove Village, IL 60007, 847-437-6400, e-mail: [email protected]
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October 2008