Digital Is a State of Mind

To a sophisticated analog signal, it must appear that digital signals have a simple life. What can be easier than going 1, 0, 1, 0…all day? That impression is true at lower speeds where a logic analyzer timing display closely resembles the real waveforms. Above several tens of megahertz, however, overshoot, slew rate, and skew effects creep in. All digital signals have these characteristics, but they often can be ignored when working with one or two low-speed logic lines.

In contrast, the timing relationships among a large number of fast digital signals are critical to many applications. The signals making up microprocessor address or data buses work so closely together that they are represented schematically as single lines.

For DAC and ADC data conversion devices, groups of digital signals represent analog values. And, interfaces between systems or subsystems involve several digital signals in a complex protocol. In all these cases, testing requires simultaneous simulation of many digital signals and their changing states over time.

A wide variety of equipment exists for this purpose. Perhaps the most specialized is a protocol exerciser, which generates a number of signals in parallel but typically for only one type of interface. You would use a PCI bus exerciser to test that specific bus. This instrument won’t help you test ADCs or DACs because it’s not sufficiently general-purpose.

A pulse pattern generator might be the instrument you need, but manufacturers have different definitions for this term. In general, the pattern part of the name refers to memory depth behind a pulse generator output. So where a simple pulse generator produces variable width pulses at a selectable rate, a pulse pattern generator is more like a 1-bit arbitrary waveform generator (Arb). The timing of the output is determined by a stored pattern.

Keithley Instruments calls its Series 3400 pulse pattern generators, and indeed you can program up to 16,384 states for each of one or two independent channels. The top speed is 165 MHz.

A digital word generator is an instrument with parallel outputs and memory. The states of the outputs can be programmed so that a series of digital words is produced. This name is well understood but not often used today. For example, the C&H Technologies MA202 is a double-wide M module 16-channel digital word generator with 32k words of memory and operation to 10 MHz.

Instead of this term, Agilent Technologies has called similar instruments, with a greater number of outputs, pulse data generators. The emphasis in this terminology is on the state of the combined outputs—the data—although this product also has memory to control the successive output values.

Tektronix calls the company’s multi-output digital instruments data timing generators. This phrase may be the most descriptive to the degree that data relates to the simultaneous states of all the outputs and timing indicates how those states change.

Regardless of the exact name, this is the type of general-purpose instrument that is needed to test today’s logic circuitry. Several manufacturers make products that may suit your needs. Tektronix and Agilent have the advantage of providing pulse pattern generators that are used with the companies’ logic analyzers. This means that you can use the same solution both to exercise and analyze the UUT.

Lower Speed Approaches

For speeds below a few megahertz, many PC plug-in data acquisition boards could be used to provide multiple digital outputs. The dSPACE Model DS4002 Timing and Digital I/O Board is a good example with eight channels dedicated to I/O timing and an additional 32 digital I/O lines. The group of eight lines is associated with an Arb-like memory system while the remaining lines must be programmed in 8-b groups by the host PC.

Output data is described as a series of rising and falling edges in the on-board timing I/O memory. There’s a loop counter and a means of altering the signal generation on the fly. This means that the DS4002 can be used as an 8-b wide pulse pattern generator. When all eight outputs are used, the minimum pulse width is 3.4 µs. The master clock rate is 5 MHz and together with 29-b pulse edge positioning results in a 100-s maximum pulse width.

Other manufacturers make similar boards that may generate eight or more bits of data based on stored delay values or simply from a much deeper memory of actual state values. Geotest-Marvin Test Systems has several digital I/O PXI modules that include 32-b wide pattern memory. Both the 6U GX5731 and 3U GX5733 Modules have on-board state pattern memories. The data sheets list the output rate as >1 kHz and the skew among channels as 10 ns typical.

The term vector memory is used to describe the pattern memory in these modules. Geotest’s use is in line with ATE jargon that considers a vector to be simply a group of related values. For example, an excerpt from a Teradyne press release reads, “With the UltraPin800, the system features up to 256 M [test] vector memory.” This is not to be confused with vector signal generators and analyzers where the word relates to I/Q modulation components.

General-purpose digital I/O lines not backed up by on-board memory must have each state programmed on the fly. The output data rate is limited by the speed at which the host PC can update the output port latches.

In practice, if several outputs are intended to change at the same time, there will be an amount of skew introduced by imperfect matching among all the output devices. If they are parts of the same IC, skew can be minimized to a few nanoseconds. However, even if the outputs were perfectly matched, unequal capacitive loading can easily create timing skew of several nanoseconds.

Because this class of board is designed for relatively low-speed applications, output channel-to-channel skew often is not specified. Nevertheless, your test timing must ensure that the outputs have all settled before being strobed into the UUT.

Faster Applications

Look for the words high speed in instrument titles if you need to generate patterns at rates faster than 10 MHz. Geotest’s high-speed dynamically controlled GX5050 Digital I/O Module essentially is a digital Arb. The dynamic part of the name refers to an on-board sequencer that supports conditional branching and looping at rates up to 50 MHz. Up to 12 MB of memory per module and configurations with as many as 16 daisy-chained modules are included.

This module and other similar Geotest dynamic or dynamically controlled PXI products are intended for use in ATE systems, digital functional test, and memory testing applications. Factory-fitted optional I/O circuitry within the modules interfaces to TTL, positive emitter coupled logic (PECL), ECL, low voltage differential signaling (LVDS), or programmable logic levels.

The VXI C-size Model 3171 Waveform and Dual Output Pulse Generator from EADS North America Defense Test and Services features a 12-b analog output clocked at up to 80 MS/s. However, all 12 bits are available as digital data backed up by the Arb’s 128-kpoint memory. Separately, two pulse generator outputs with programmable rise/fall times run at up to a 50-MHz rate.

Above several tens of megahertz, TTL or CMOS levels become less appropriate because of the very high slew rates needed. TTL has lots of variants, but for a 5-V supply, many types of TTL recognize a minimum 1.2-V swing between 0.8 V and 2.0 V although they generate a 0.35-V to 3.3-V output swing. CMOS typically has an even larger swing, with TTL-compatible CMOS between the CMOS and TTL levels.

ECL and PECL swings are only 0.8 V, and even generic versions of these families easily operate at 100 MHz. However, newer high-speed interfaces often use LVDS differential pairs with 350-mV swings. LVDS interfaces are capable of reliable operation at much higher rates. For example, the Maxim MAX9174/5 LVDS-to-LVDS 1:2 Splitter is rated to 670 MHz.

National Instruments (NI) makes the PXI-6561/2 Digital Waveform Generator/Analyzer—yet another name for a pulse pattern generator. The 6561 inputs or outputs from 1-b to 16-b data at up to 100 MS/s in the single data rate (SDR) mode or 200 MS/s in the double data rate (DDR) mode. With DDR selected, one 8-b port is dedicated to inputs and the other 8-b port to outputs. The 6562 runs at 200 MS/s in the SDR mode and 400 MS/s in DDR. Channel-to-channel skew typically is 215 ps, 450 ps maximum.

If you need fewer than 16 outputs, the built-in hardware compare capability can be used to detect differences between input data from your device under test and stored expected values.

In single-waveform mode, a waveform is produced once, n times, or continuously. In scripted mode, a simple or complex sequence of waveforms can be output. Scripts describe the waveforms to be generated, the order in which they are generated and how many times, and how the generator responds to script triggers. Up to 128 Mb of memory support each channel.

Data generation at these rates requires careful attention to transmission line details. LVDS solves part of the problem by operating the output lines at very low levels, which develops less crosstalk and smaller reflections. Further, the large common-mode range on LVDS inputs means that most of a system’s common-mode signal impairments will be ignored.

In addition, the PXI-6561/2 modules specify 50-? SMB jacks for the external input clock, exported reference and output clocks, and triggers. The 16 bits of actual data run on a 12X InfiniBand connector. Because InfiniBand is a full-duplex interface that uses two twisted pairs for each channel, 24 pairs of pins are available on the 12X connector. Each pair is positioned between large ground pins to reduce crosstalk and maintain the 100-? characteristic.

Strategic Test offers the Model UF2-7000 64-b High-Speed Digital I/O Board with either a PCI or PXI Express interface. Up to 16 boards per system and up to 271 boards in 17 PCs can be synchronized. Each board generates from 1- to 64-b data to 60 MS/s or 32 b at 125 MS/s. Standard memory depth is 256 MB but can be increased to 4 GB. In addition, high, sustained output rates are supported by PC-to-board streaming at up to 120 MB/s.

The PG3A Digital Pattern Generator is sold by Tektronix but made by The Moving Pixel Company. This instrument supports up to 64 channels with a 32-Mvector memory and provides ±150-ps skew at a maximum 300-MHz data rate.

Output connections are via 16 signal probes and need to be differentially terminated in 100 ?. The P373 LVDS Probe provides the maximum 300-MHz rate while three versions of the P370 TTL/CMOS Probe match a wide range of logic levels at speeds up to 150 MHz or 200 MHz.

Agilent’s 48-channel Model 16720A Pattern Generator Module plugs into the company’s 16700 and 16900 Series Logic Analyzers. A maximum of five modules can be linked for 16 Mvectors 240-b wide at 180 MHz or eight Mvectors 120-b wide at 300 MHz. Several output pods support TTL, CMOS, ECL, PECL, low voltage PECL (LVPECL), and LVDS logic levels. A typical configuration with the Model 10473A 3-State Data Pod is shown in Figure 1.

Having a deep memory means that detailed design simulation files can be used as stimulus patterns, either to exercise obscure operating modes or to simulate part of a larger system. Because the pattern generator is integrated with the logic analyzer, you can immediately determine if the circuit under test is functioning as expected.

If your application requires only 8-b or 16-b data, a small, PC-based waveform generator might be appropriate. The ETC M631 with the A631 option develops 16-b data at up to a 50-MHz rate backed up by 256-kwords of memory.

Acute Technology’s Model PKPG-2116 also outputs 16-b data but at rates to 200 Mb/s and backed up by 512-kvector memory. Byte Paradigm’s Wave Generator Xpress generates 16-b data at up to a 50-MHz rate but can output as much as a 100-MB arbitrary pattern directly from the host PC. The Acute Technology and Byte Paradigm instruments are powered by and interface through high-speed USB 2.0.

In all these instruments, accurate timing is a concern because differences in cable delays or device speeds that could be ignored at slower speeds no longer can be. NI’s Scott Savage, product manager high-speed digital I/O, commented, “Data delay is an important feature that gives an engineer the ability to skew data by a portion of the clock period to adjust for custom timing requirements or delays introduced by PCB traces or cables.

“Customers typically use data delay to implement custom protocols by varying the position of digital edges or for basic data alignment from delays
in the signal path,” he explained. “Some customers sweep data delay values to characterize aspects of their device under test.”

Really Fast Applications

The Tektronix DTG5000 Series of data timing generators comes in three speeds: the DTG5078 to 750 Mb/s, the DTG5274 to 2.7 Gb/s, and the DTG5334 to 3.35 Gb/s. Selectable internal modules determine the number and type of outputs available. Not surprisingly, more channels are available at lower speeds. Figure 2 shows a Series DTG5000 Generator being used in a typical test/debug setup.

In the DTG5078, 96 channels are possible by linking three mainframes. Each mainframe can have eight DTGM21 internal modules with four single-ended outputs on SMA connectors. At the higher speeds, only two mainframes can be linked, and the output modules support a maximum of 16 single-ended or 16 complementary channels with SMA connectors.

Channel-to-channel skew is as low as 100 ps after semi-automatic deskew calibration. Signals can be delayed from zero to 5 ns with 1-ps resolution in the DTG5078 and 0.2-ps resolution in the other two models. Very large pattern memories are possible.

Because the generators are intended for compliance and interoperability applications as well as more general-purpose use, several test patterns are built in. These include binary, Johnson, and Graycode counters; walking ones and walking zeros; and checker board. You also can define your own patterns and import data with a variety of file formats. Several interfaces and storage media can be used: GPIB, LAN, CD-ROM, floppy drive, and USB memory devices.

Even Faster Than That

Rather than attempting to maintain alignment among parallel channels at higher and higher speeds, most interfaces have opted for serial buses. Several lanes may be required, but each one operates independently with its own embedded clock so skew across eight or 16 lanes isn’t important.

Nevertheless, speeds of several gigahertz cause their own problems. At such high data rates, most transmission channels act like low-pass filters, reducing the amplitude of the highest frequencies. Naturally, this greatly affects the data edges, causing loss of definition. Individual data bits spread in time, producing intersymbol interference (ISI) that can make it very difficult for a receiver to distinguish a zero from a one.

Boosting the level of the first one or zero in a block of like bits is called pre-emphasis and counteracts signal degradation caused by limited channel bandwidth. A related term, de-emphasis, describes the reduction in amplitude applied to the ones or zeros immediately following the initial bit.

Pre/de-emphasis is achieved in several ways, all of which are equivalent to a finite impulse response (FIR) filter. SyntheSys Research recently introduced the BERTScope™ Digital Pre-Emphasis Processor (DPP), which performs either three- or four-tap FIR filtering on serial bit streams at rates to 12.5 Gb/s. By changing the weighting of the taps, the pre-emphasis requirements of 10GbE, PCI Express, SAS 6Gb/s, and USB 3.0 standards can
be accommodated.

A Tektronix technical brief explains a two-tap form of pre-emphasis that can be used with one of the company’s data timing generators. If the pattern for output 1 is delayed by one clock period and stored as the pattern for output 2, this pair of signals will be identical except one will lag the other.

Figure 3a was generated by subtracting 20% of a delayed version from 100% of the original signal. With a data timing generator, external circuitry is needed to do this.¹ In an FIR filter, the same process occurs, but the delayed version of the signal and the weighting are combined in the filter.

A three-tap filter can account for aberrations caused to the next symbol as well as those resulting from the previous one. Having more taps becomes important at higher speeds or with lower bandwidth channels as the data becomes less distinct.

Figure 3b shows the additional effect of also subtracting 10% of the same data pattern advanced by one bit period. You can’t advance the data pattern, but it’s equivalent to use two stages of delay in an FIR filter. The concepts of earlier and later in time are with reference to the center tap.

By boosting the signal level of the transitions, a more distinct pulse appears at the receiver. Alternatively, the third tap can be used to more precisely compensate for just the effects of the previous pulse.

Software accompanying the SyntheSys Research DPP helps you establish the proper weighting for the filter taps and displays simulated signal waveforms as well as a Bode plot of the filter’s frequency response.²

Summary

As speeds continue to increase, engineers have been reminded that all signals actually are analog. It’s just a convenient abstraction to treat some signals as having only two states. When digital data exhibits obvious analog characteristics, either by degradation or intentionally, Arbs become appropriate generators. Especially for compliance testing that specifies certain types and amounts of serial data impairments for receiver testing, a very high-speed Arb can simplify signal generation.

Nevertheless, for parallel data applications, many digital word/timing generators are available with good performance up to a few hundred megahertz. A much smaller number of instruments operate into the gigahertz region.

These kinds of products can simulate parts of a system that haven’t yet been developed. They provide corner test cases: data values that a system or ASIC might never encounter but still must respond to in a defined way. In an automotive example, spark-plug firing and fuel-injector drive signals can be simulated during engine development.

Todd Stocker, marketing manager at Keithley Instruments, commented, “Historically, the first generation of pulse/pattern instruments was designed to facilitate telecomms device testing. In the second phase, designers turned their attention to PC backplane data communications such as the parallel PCI bus. More recently, the emphasis has been on embedded serial buses.”

The need for parallel-output digital pattern generators hasn’t gone away. They’re simply being used for different purposes.

Reference

1. Analog Signals Join Digital Patterns in Serial Data Receiver Tests, Technical Brief, Tektronix, 2006.
2. Nakatani, C., Combating Closed Eyes: Pre-Emphasis and Equalization Basics, Technical Note TN073, SyntheSys Research, 2008.

November 2008