The AXIe (AdvancedTCA® extensions for instrumentation and test) Consortium was launched in November 2009 to develop and promote the AXIe Standard. Within eight months, the membership had grown 270%, and the first specifications were released to the test and measurement and semiconductor ATE markets: AXIe 1.0 Base Architecture Specification, Rev. 1.0 and AXIe 3.1: Semiconductor Test Extension, Rev. 1.0. By the end of 2010, the first AXIe products were introduced.
AXIe not only leverages existing standards (AdvancedTCA, LXI, PXI, IVI) in both architecture and use model, but AXIe devices also integrate easily on the system level with GPIB instrumentation. The emerging standard promises higher speeds, more scalability, more cost savings per rack inch, and better power management than current test standards.
AXIe 1.0 is focused on the general-purpose test and measurement market, and AXIe 3.1 was developed for the semiconductor ATE market. AXIe is a layered specification so semiconductor instruments and systems using 3.1 can integrate with AXIe 1.0 instruments.
In 2011, the AXIe Technical Committee continues its aggressive pace with a number of proposals to enhance the value of the specifications for instrument vendors, system designers and integrators, and test engineers.
AXIe 2.0: Software Specification
The AXIe 2.0 Software Specification will define the software configuration requirements of chassis and systems. This includes hybrid systems containing both AXIe and PXI or PXIe.
The goal will be to provide a satisfying experience for system integrators and test engineers using AXIe 1.0 equipment. This specification will incorporate features and best practices from existing instrumentation software specifications such as AdvancedTCA, PXI, LXI, and IVI and describe software features and interfaces specifically for supporting AXIe 1.0 hardware.
Regarding PXI, the goal will be to maintain a high degree of compatibility with the existing PXI infrastructure. This includes the capabilities for discovering and describing system configurations, their chassis, and modules installed for use with PCIe or support software addressing AXIe instruments with PXI conventions.
With LXI, AXIe 2.0 will extend system configurations for supporting access to LXI instrumentation. Supporting Intelligent Platform Management Interface (IPMI) communications for AdvancedTCA chassis management and field-replaceable unit inventory will be a priority as well as describing software frameworks for AXIe and common APIs.
The Technical Committee plans to write system configuration discovery tooldefinitions which make it simple for customers to interact with their module and systems. They will be able to easily describe a system instrument module, trigger routing and local bus mapping, or mapping a PXI card into a carrier.
These specifications would help with resource management to enumerate PCIe-only, LAN-only, and PCIe/LAN mixed instruments or develop nomenclature that allows for AXIe targeted extensions, such as the current 3.1 specifications, or API definitions. These ideas along with board- and shelf-management control specifications will provide the foundation for building instruments that simplify the tasks of a system integrator.
AXIe 2.1: Software Specification
The AXIe 2.1: Software Specification will define requirements for multisite programming features appropriate for semiconductor production test applications. It will specify software requirements, architecture, and methodologies used to create Multisite Virtual Pin (MVP-C)-compliant instrumentation, control APIs, and instrument drivers. The instrument control APIs will be modeled after IVI-C class APIs.
The AXIe 2.1 specification provides the following:
- Interchangeable instrumentation hardware without software recompile
- Consistent and simple programming model
- Support for multiple programming environments
- A standard computer interface
- High-performance execution
- Multisite scalability and virtual instrument addressing
- Instrument addressing to the DUT interface board
- Minimal and modular software updates
MicroTCA and Serial Rapid I/O
Two elements are of high interest to the base AdvancedTCA architecture for advanced processing functions: the use of an AXIe carrier card, which would allow both commercial and specialized MicroTCA processor cards to be incorporated into an AXIe system; and the serial rapid I/O (sRIO) high-speed data bus in addition to PCIe in the AXIe bus structure. Both capabilities would increase the AXIe processing power and associated data transport bus fabric.
This year, exciting enhancements are planned for the AXIe 1.0 and 3.1 hardware specifications aimed at the general-purpose test and measurement and semiconductor ATE markets that increase the speed, flexibility, and ease of use in the emerging AXIe standard.
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